Inventor · disambiguated record
Andrew A. Turner
Also filed as: TURNER ANDREW · TURNER ANDREW A
21 granted patents·1 pending application·31 citations·filing 2012–2022
91Inventor score
Top patents by PatentIndex Score
22 records- 0196US9588177B1Optimizing generation of test configurations for built-in self-testingIBM·Filed 2016·Granted Mar 7, 2017·17 cites·20 claims
- 0286US11146251B2Performance-screen ring oscillator with switchable featuresIBM·Filed 2020·Granted Oct 12, 2021·2 cites·15 claims
- 0383US11989071B2Dynamic guard band with timing protection and with performance protectionIBM·Filed 2022·Granted May 21, 2024·1 cites·20 claims
- 0477US10101388B2Method for enhanced semiconductor product diagnostic fail signature detectionIBM·Filed 2015·Granted Oct 16, 2018·2 cites·19 claims
- 0573US9712112B1Dynamic noise mitigation in integrated circuit devices using local clock buffersIBM·Filed 2016·Granted Jul 18, 2017·1 cites·20 claims
- 0671US11226372B2Portable chip tester with integrated field programmable gate arrayIBM·Filed 2019·Granted Jan 18, 2022·1 cites·19 claims
- 0771US9733307B1Optimized chain diagnostic fail isolationIBM·Filed 2016·Granted Aug 15, 2017·1 cites·11 claims
- 0871US9087841B2Self-correcting power grid for semiconductor structures methodIBM·Filed 2013·Granted Jul 21, 2015·2 cites·10 claims
- 0969US10726178B1Functional logic cone signature generation for circuit analysisIBM·Filed 2019·Granted Jul 28, 2020·2 cites·20 claims
- 1063US8586444B2Creating deep trenches on underlying substrateAPPLEYARD JENNIFER E·Filed 2012·Granted Nov 19, 2013·2 cites·9 claims
- 1158US10768226B2Testing mechanism for a proximity fail probability of defects across integrated chipsIBM·Filed 2018·Granted Sep 8, 2020·0 cites·16 claims
- 1254US8860113B2Creating deep trenches on underlying substrateIBM·Filed 2013·Granted Oct 14, 2014·0 cites·14 claims
- 1353US11953982B2Dynamic guard band with timing protection and with performance protectionIBM·Filed 2022·Granted Apr 9, 2024·0 cites·20 claims
- 1451US10215804B2Semiconductor power and performance optimizationIBM·Filed 2016·Granted Feb 26, 2019·0 cites·20 claims
- 1551US10114071B2Testing mechanism for a proximity fail probability of defects across integrated chipsIBM·Filed 2016·Granted Oct 30, 2018·0 cites·13 claims
- 1650US2018136273A1Method and Apparatus for Offline Supported Adaptive TestingIBM·Filed 2018·Application pending·0 cites
- 1747US9921264B2Method and apparatus for offline supported adaptive testingIBM·Filed 2016·Granted Mar 20, 2018·0 cites·1 claims
- 1847US9214427B2Method of self-correcting power grid for semiconductor structuresIBM·Filed 2015·Granted Dec 15, 2015·0 cites·17 claims
- 1944US11169841B2Tunable power save loop for processor chipsIBM·Filed 2020·Granted Nov 9, 2021·0 cites·17 claims
- 2042US9575115B2Methodology of grading reliability and performance of chips across waferGLOBALFOUNDRIES INC·Filed 2012·Granted Feb 21, 2017·0 cites·19 claims
- 2142US9557381B1Physically aware insertion of diagnostic circuit elementsIBM·Filed 2016·Granted Jan 31, 2017·0 cites·18 claims
- 2234US9008196B2Updating interface settings for an interfaceANGELOTTI FRANK W·Filed 2012·Granted Apr 14, 2015·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →