Creating deep trenches on underlying substrate

Abstract

A semiconductor structure and method of fabricating the same are disclosed. In an embodiment, the structure includes a first substrate having a buried plate or plates in the substrate. Each buried plate includes at least one buried plate contact, and a plurality of deep trench capacitors disposed about the at least one buried plate contact. A first oxide layer is disposed over the first substrate. The deep trench capacitors and buried plate contacts in the first substrate may be accessed for use in a variety of memory and decoupling applications.

What is claimed is: 
     
       1. A method comprising:
 providing a first substrate; 
 doping an upper part of the first substrate to form at least one buried plate in the first substrate; 
 forming a plurality of trenches in each of the at least one buried plate; and 
 filling each of the plurality of trenches with a first conductor to form an inner electrode in each of the plurality of trenches; 
 providing a second substrate, wherein the second substrate includes an oxide layer on a bottom surface thereof, and a layer of implanted hydrogen disposed partway through a thickness of the second substrate; 
 bonding the oxide layer on the bottom surface of the second substrate to the oxide layer disposed over the upper surface of the first substrate; and 
 
       removing a portion of the second substrate disposed above the layer of implanted hydrogen. 
     
     
       2. The method of  claim 1 , further comprising:
 forming a recess in an upper surface of the first conductor in each of the plurality of trenches; 
 depositing polysilicon over the upper surface of the first conductor and an upper surface of the first substrate; and 
 removing the polysilicon from the upper surface of the first substrate. 
 
     
     
       3. The method of  claim 1 , further comprising:
 before filling the plurality of trenches with the first conductor, 
 forming an oxide liner in each of the plurality of trenches; and 
 forming an oxide layer over the upper surface of the first substrate, 
 wherein each of the plurality of inner electrodes extends vertically above an upper surface of the at least one buried plate. 
 
     
     
       4. The method of  claim 3 , further comprising:
 after forming an oxide liner in each of the plurality of trenches, 
 forming a mask layer over some of the plurality of trenches in each of the at least one buried plate, wherein at least one of the plurality of trenches is not covered by the mask; 
 etching the oxide liner from the exposed at least one of the plurality of trenches; and 
 removing the mask. 
 
     
     
       5. The method of  claim 1 , further comprising:
 providing a polyconductor gate disposed above the second substrate; 
 depositing a second oxide layer above the second substrate; and 
 forming a plurality of contact trenches extending from an upper surface of the second oxide layer to each of the plurality of first conductors. 
 
     
     
       6. The method of  claim 5 , further comprising:
 depositing a resist layer over the second oxide layer and in the plurality of trenches extending from the surface of the second oxide layer to each of the plurality of first conductors, forming a mask having openings disposed above the second substrate; 
 etching the second oxide layer to form contact trenches vertically extending from the surface of the second oxide layer to the second substrate; and 
 removing the resist layer. 
 
     
     
       7. The method of  claim 6 , further comprising:
 depositing a conductive contact in the plurality of contact trenches to form contacts with each of the plurality of first conductors and the second substrate. 
 
     
     
       8. The method of  claim 6 , further comprising:
 before depositing the conductive contact in the plurality of contact trenches, 
 depositing a liner on a sidewall and a bottom surface of each of the plurality of trenches. 
 
     
     
       9. The method of  claim 8 , wherein the conductive contact further comprises tungsten, and the liner further comprises one of titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), and tungsten silicide (WSi 2 ).