Inventor · disambiguated record
Fernand Dorleans
Also filed as: DORLEANS FERNAND · DORLEANS FERNAND J
10 granted patents·1 pending application·611 citations·filing 1988–2002
93Inventor score
Top patents by PatentIndex Score
11 records- 0194US5763851ASlotted RF coil shield for plasma deposition systemAPPLIED MATERIALS INC·Filed 1996·Granted Jun 9, 1998·93 cites·64 claims
- 0292US5985759AOxygen enhancement of ion metal plasma (IMP) sputter deposited barrier layersAPPLIED MATERIALS INC·Filed 1998·Granted Nov 16, 1999·120 cites·14 claims
- 0391US6271592B1Sputter deposited barrier layersAPPLIED MATERIALS INC·Filed 1999·Granted Aug 7, 2001·104 cites·14 claims
- 0488US5658442ATarget and dark space shield for a physical vapor deposition systemAPPLIED MATERIALS INC·Filed 1996·Granted Aug 19, 1997·105 cites·6 claims
- 0582US5633522ACMOS transistor with two-layer inverse-T tungsten gateIBM·Filed 1996·Granted May 27, 1997·60 cites·12 claims
- 0680US6448657B1Structure for reducing junction spiking through a wall surface of an overetched contact viaAPPLIED MATERIALS INC·Filed 2000·Granted Sep 10, 2002·21 cites·12 claims
- 0770US5599725AMethod for fabricating a MOS transistor with two-layer inverse-T tungsten gate structureIBM·Filed 1994·Granted Feb 4, 1997·40 cites·11 claims
- 0869US5340775AStructure and fabrication of SiCr microfusesIBM·Filed 1993·Granted Aug 23, 1994·40 cites·12 claims
- 0950US5285099ASiCr microfusesIBM·Filed 1992·Granted Feb 8, 1994·17 cites·4 claims
- 1044US4900274AKeying system for assuring proper array configuration of cable cardsIBM·Filed 1988·Granted Feb 13, 1990·11 cites·9 claims
- 1140US2002175420A1Method of reducing junction spiking through a wall surface of an overetched contact viaFiled 2002·Application pending·0 cites
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