Inventor

BONIFIELD THOMAS D

US47 patents

⚠️ This page may combine multiple inventors who share the name “BONIFIELD THOMAS D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BONIFIELD THOMAS D

TEXAS INSTRUMENTS INC

High breakdown voltage microelectronic device isolation structure with improved reliability

Planarized selective tungsten metallization system

Plasma reactor sidewall shield

Metallization process for a semiconductor device

Oxide etch

High breakdown voltage microelectronic device isolation structure with improved reliability

TSVS having chemically exposed TSV tips for integrated circuit devices

Plasma reactor with reduced chamber wall deposition

Nickel alloy silicide including indium and a method of manufacture therefor

Nickel alloy silicide including indium and a method of manufacture therefor

Nickel silicide including indium and a method of manufacture therefor

Contact etch method

Nickel silicide including indium and a method of manufacture therefor

Hybrids semiconductor circuit

Semiconductor hybrids and method of making same

Isolation substrate ring for plasma reactor

High voltage galvanic isolation device

High breakdown voltage microelectronic device isolation structure with improved reliability

Methods and apparatus for high voltage integrated circuit capacitors

Device isolator with reduced parasitic capacitance

Mask overhang reduction or elimination after substrate etch

Planarized selective tungsten metallization system

Methods and apparatus for high voltage integrated circuit capacitors

Device isolator with reduced parasitic capacitance

Device isolator with reduced parasitic capacitance

Semiconductor hybrids and method of making same

Scribe seal connection

Hybrid isolation capacitors in series

Hybrid high and low stress oxide embedded capacitor dielectric

Scribe seals and methods of making

High voltage galvanic isolation device

Device isolator with reduced parasitic capacitance

Method for fabricating a multi-level integrated circuit having scatterometry test structures stacked over same footprint area

Integrated capacitor with sidewall having reduced roughness

Generating multi-focal defect maps using optical tools

Integrated capacitor with sidewall having reduced roughness

Hydrogen ventilation of CMOS wafers

Method of preventing seam defects in isolated lines

Methods and apparatus for high voltage integrated circuit capacitors

Crack deflector structure for improving semiconductor device robustness against saw-induced damage

Method of fabricating a thick oxide feature on a semiconductor wafer

Metal silicide induced lateral excessive encroachment reduction by silicon &lt;110&gt; channel stuffing

DUNNE RAJIV

IC device having low resistance TSV comprising ground connection

IC device having low resistance TSV comprising ground connection

IC device having low resistance TSV comprising ground connection

WEST JEFFREY ALAN

Crack deflector structure for improving semiconductor device robustness against saw-induced damage

BONIFIELD THOMAS D

Packaged electronic devices with face-up die having TSV connection to leads and die pad

Metal silicide induced lateral excessive encroachment reduction by silicon <110> channel stuffing