US8431481B2ActiveUtilityA1

IC device having low resistance TSV comprising ground connection

79
Assignee: DUNNE RAJIVPriority: May 12, 2008Filed: Apr 11, 2012Granted: Apr 30, 2013
Est. expiryMay 12, 2028(~1.8 yrs left)· nominal 20-yr term from priority
H10W 90/756H10W 90/754H10W 90/736H10W 90/734H10W 90/732H10W 90/726H10W 90/722H10W 90/297H10W 74/15H10W 72/942H10W 72/884H10W 72/879H10W 72/859H10W 72/354H10W 72/352H10W 72/325H10W 72/29H10W 90/811H10W 90/00H10W 72/30H10W 20/20H10W 20/0249H10W 72/952H10W 70/417
79
PatentIndex Score
4
Cited by
2
References
11
Claims

Abstract

A method of forming a semiconductor device includes an integrated circuit (IC) die which is provided with a substrate with surfaces. At least one through substrate via (TSV) is formed through the substrate to a protruding integral tip that includes sidewalls and a distal end. A metal layer is formed on the bottom surface of the IC die, and the sidewalls and the distal end of the protruding integral tips. Completing fabrication of at least one functional circuit including at least one ground pad on the top surface of the semiconductor, wherein the ground pad is coupled to said TSV.

Claims

exact text as granted — not AI-modified
We claim: 
     
       1. A method of forming a semiconductor device including an integrated circuit (IC) die, comprising:
 providing a substrate having a top semiconductor comprising surface and a bottom surface; 
 forming at least one through substrate via (TSV) comprising a first electrically conductive composition extending from said top semiconductor surface through said substrate to a protruding integral tip comprising sidewalls and a distal end opposite said bottom surface, having a tip height of between 1 and 50 μm; 
 forming a metal layer on said bottom surface of said IC die, and said sidewalls and said distal end of said protruding integral tip, said metal layer comprising a second electrically conductive metal comprising composition that is different from said first electrically conductive composition, and 
 completing fabrication of at least one functional circuit including at least one ground pad on said top semiconductor comprising surface, wherein said ground pad is coupled to said TSV. 
 
     
     
       2. The method of  claim 1 , wherein said forming said metal layer comprises electrolessly plating. 
     
     
       3. The method of  claim 2 , wherein said metal layer comprises a continuous metal layer that extends over an entire area of said bottom surface of said IC die. 
     
     
       4. The method of  claim 1 , wherein said second electrically conductive metal comprising composition comprises a solder or solder alloy. 
     
     
       5. The method of  claim 4 , further comprising reflowing said solder or solder alloy to provide a thickness of said solder or said solder alloy that is thicker at a center of said IC die as compared to a periphery of said IC die to provide a dome shape thickness profile. 
     
     
       6. The method of  claim 3 , further comprising forming an electrically conductive adhesive layer comprising a third electrically conductive composition on said metal layer, said third electrically conductive composition being compositionally different from said first electrically conductive composition and said second electrically conductive composition. 
     
     
       7. The method of  claim 6 , wherein said electrically conductive adhesive layer comprises a metal filled polymer, said metal filled polymer providing a room temperature bulk resistivity <500 μohm·cm. 
     
     
       8. The method of  claim 1 , further comprising forming a liner on said sidewalls comprising a material different from said first and said second electrically conductive compositions that extends beyond said bottom surface a distance of at least 1% of said tip height, wherein said metal layer is on top of said liner. 
     
     
       9. The method of  claim 8 , wherein said TSV comprises a plurality of said TSVs, and wherein said protruding integral tip from two or more of said plurality of TSVs are shorted together by said metal layer to provide a ground connection for active circuitry formed on said top semiconductor comprising surface IC die. 
     
     
       10. The method of  claim 1 , further comprising:
 providing a package substrate having a top metal comprising surface, and 
 mounting said IC die face up on said package substrate, wherein said metal layer provides a portion of an electrical ground connection for said IC die through coupling said TSV to said top metal comprising surface. 
 
     
     
       11. The method of  claim 10 , wherein said package substrate comprises a lead frame comprising a die paddle, and wherein second electrically conductive metal comprising composition comprises a solder or solder alloy, wherein said solder or solder alloy is bonded directly to said die paddle.

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