Inventor · disambiguated record
Son Hung Tran
Also filed as: TRAN SON H · TRAN SON HUNG
17 granted patents·6 pending applications·77 citations·filing 2016–2025
93Inventor score
Files withTEXAS INSTRUMENTS INC23
Top patents by PatentIndex Score
23 records- 0196US11269638B2Exposing valid byte lanes as vector predicates to CPUTEXAS INSTRUMENTS INC·Filed 2017·Granted Mar 8, 2022·18 cites·33 claims
- 0296US11249842B2Error correcting codes for multi-master memory controllerTEXAS INSTRUMENTS INC·Filed 2020·Granted Feb 15, 2022·4 cites·20 claims
- 0395US11768733B2Error correcting codes for multi-master memory controllerTEXAS INSTRUMENTS INC·Filed 2022·Granted Sep 26, 2023·2 cites·20 claims
- 0495US11231929B2One-dimensional zero padding in a stream of matrix elementsTEXAS INSTRUMENTS INC·Filed 2019·Granted Jan 25, 2022·14 cites·20 claims
- 0594US11941399B2Exposing valid byte lanes as vector predicates to CPUTEXAS INSTRUMENTS INC·Filed 2022·Granted Mar 26, 2024·2 cites·20 claims
- 0694US11113062B2Inserting predefined pad values into a stream of vectorsTEXAS INSTRUMENTS INC·Filed 2019·Granted Sep 7, 2021·10 cites·19 claims
- 0793US12118358B2One-dimensional zero padding in a stream of matrix elementsTEXAS INSTRUMENTS INC·Filed 2022·Granted Oct 15, 2024·2 cites·18 claims
- 0893US11249759B2Two-dimensional zero padding in a stream of matrix elementsTEXAS INSTRUMENTS INC·Filed 2019·Granted Feb 15, 2022·13 cites·20 claims
- 0991US11256508B2Inserting null vectors into a stream of vectorsTEXAS INSTRUMENTS INC·Filed 2019·Granted Feb 22, 2022·10 cites·20 claims
- 1089US2025362913A1Exposing valid byte lanes as vector predicates to cpuTEXAS INSTRUMENTS INC·Filed 2025·Application pending·0 cites
- 1186US10901913B2Two address translations from a single table look-aside buffer readTEXAS INSTRUMENTS INC·Filed 2019·Granted Jan 26, 2021·1 cites·18 claims
- 1285US11907721B2Inserting predefined pad values into a stream of vectorsTEXAS INSTRUMENTS INC·Filed 2021·Granted Feb 20, 2024·1 cites·20 claims
- 1382US12379925B2Exposing valid byte lanes as vector predicates to CPUTEXAS INSTRUMENTS INC·Filed 2024·Granted Aug 5, 2025·0 cites·20 claims
- 1482US2025390438A1Two address translations from a single table look-aside buffer readTEXAS INSTRUMENTS INC·Filed 2025·Application pending·0 cites
- 1581US12204905B2Inserting predefined pad values into a stream of vectorsTEXAS INSTRUMENTS INC·Filed 2024·Granted Jan 21, 2025·0 cites·20 claims
- 1679US2025036411A1Padding in a stream of matrix elementsTEXAS INSTRUMENTS INC·Filed 2024·Application pending·0 cites
- 1778US12235773B2Two address translations from a single table look-aside buffer readTEXAS INSTRUMENTS INC·Filed 2021·Granted Feb 25, 2025·0 cites·19 claims
- 1876US2024378058A1Two-dimensional zero padding in a stream of matrix elementsTEXAS INSTRUMENTS INC·Filed 2024·Application pending·0 cites
- 1975US2025156185A1Inserting predefined pad values into a stream of vectorsTEXAS INSTRUMENTS INC·Filed 2025·Application pending·0 cites
- 2071US2017132149A1Two address translations from a single table look-asside buffer readTEXAS INSTRUMENTS INC·Filed 2016·Application pending·0 cites
- 2169US12045617B2Two-dimensional zero padding in a stream of matrix elementsTEXAS INSTRUMENTS INC·Filed 2022·Granted Jul 23, 2024·0 cites·27 claims
- 2268US11782718B2Implied fence on stream openTEXAS INSTRUMENTS INC·Filed 2021·Granted Oct 10, 2023·0 cites·20 claims
- 2363US10963255B2Implied fence on stream openTEXAS INSTRUMENTS INC·Filed 2019·Granted Mar 30, 2021·0 cites·22 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →