Inventor · disambiguated record
David V. Horak
Also filed as: HORAK DAVID · HORAK DAVID V · HORAK DAVID VACLAV
365 granted patents·35 pending applications·8,712 citations·filing 1996–2022
99Inventor score
Top patents by PatentIndex Score
400 records- 0199US8482132B2Pad bonding employing a self-aligned plated liner for adhesion enhancementYANG CHIH-CHAO·Filed 2009·Granted Jul 9, 2013·237 cites·6 claims
- 0299US7528494B2Accessible chip stack and process of manufacturing thereofIBM·Filed 2005·Granted May 5, 2009·258 cites·16 claims
- 0399US7351648B2Methods for forming uniform lithographic featuresIBM·Filed 2006·Granted Apr 1, 2008·163 cites·20 claims
- 0499US7084060B1Forming capping layer over metal wire structure using selective atomic layer depositionIBM·Filed 2005·Granted Aug 1, 2006·637 cites·16 claims
- 0599US6440801B1Structure for folded architecture pillar memory cellIBM·Filed 2000·Granted Aug 27, 2002·199 cites·13 claims
- 0698US9064801B1Bi-layer gate cap for self-aligned contact formationIBM·Filed 2014·Granted Jun 23, 2015·49 cites·17 claims
- 0798US8785284B1FinFETs and fin isolation structuresIBM·Filed 2013·Granted Jul 22, 2014·34 cites·18 claims
- 0898US8084311B1Method of forming replacement metal gate with borderless contact and structure thereofHORAK DAVID V·Filed 2010·Granted Dec 27, 2011·57 cites·20 claims
- 0998US8004024B2Field effect transistorIBM·Filed 2009·Granted Aug 23, 2011·106 cites·27 claims
- 1098US6875703B1Method for forming quadruple density sidewall image transfer (SIT) structuresIBM·Filed 2004·Granted Apr 5, 2005·286 cites·9 claims
- 1198US6864041B2Gate linewidth tailoring and critical dimension control for sub-100 nm devices using plasma etchingIBM·Filed 2001·Granted Mar 8, 2005·538 cites·12 claims
- 1298US6713835B1Method for manufacturing a multi-level interconnect structureIBM·Filed 2003·Granted Mar 30, 2004·297 cites·39 claims
- 1398US6225158B1Trench storage dynamic random access memory cell with vertical transfer deviceIBM·Filed 1998·Granted May 1, 2001·197 cites·7 claims
- 1498US6114725AStructure for folded architecture pillar memory cellIBM·Filed 1998·Granted Sep 5, 2000·160 cites·11 claims
- 1597US8772168B2Formation of the dielectric cap layer for a replacement gate structureXIE RUILONG·Filed 2012·Granted Jul 8, 2014·34 cites·7 claims
- 1697US8299625B2Borderless interconnect line structure self-aligned to upper and lower level contact viasPONOTH SHOM·Filed 2010·Granted Oct 30, 2012·45 cites·11 claims
- 1796US9177820B2Sub-lithographic semiconductor structures with non-constant pitchIBM·Filed 2012·Granted Nov 3, 2015·20 cites·12 claims
- 1896US8906807B2Single fin cut employing angled processing methodsIBM·Filed 2012·Granted Dec 9, 2014·23 cites·20 claims
- 1996US8492274B2Metal alloy cap integrationIBM·Filed 2012·Granted Jul 23, 2013·19 cites·9 claims
- 2096US8390079B2Sealed air gap for semiconductor chipHORAK DAVID V·Filed 2010·Granted Mar 5, 2013·26 cites·4 claims
- 2196US8298954B1Sidewall image transfer process employing a cap material layer for a metal nitride layerARNOLD JOHN C·Filed 2011·Granted Oct 30, 2012·29 cites·20 claims
- 2296US8288268B2Microelectronic structure including air gapEDELSTEIN DANIEL C·Filed 2010·Granted Oct 16, 2012·24 cites·20 claims
- 2396US8232618B2Semiconductor structure having a contact-level air gap within the interlayer dielectrics above a semiconductor device and a method of forming the semiconductor structure using a self-assembly approachBREYTA GREGORY·Filed 2010·Granted Jul 31, 2012·33 cites·12 claims
- 2496US7362412B2Method and apparatus for cleaning a semiconductor substrate in an immersion lithography systemIBM·Filed 2004·Granted Apr 22, 2008·62 cites·26 claims
- 2596US7351666B2Layout and process to contact sub-lithographic structuresIBM·Filed 2006·Granted Apr 1, 2008·36 cites·13 claims
- 2696US7276768B2Semiconductor structures for latch-up suppression and methods of forming such semiconductor structuresIBM·Filed 2006·Granted Oct 2, 2007·30 cites·8 claims
- 2795US9935168B2Gate contact with vertical isolation from source-drainIBM·Filed 2017·Granted Apr 3, 2018·8 cites·20 claims
- 2895US8916337B2Dual hard mask lithography processARNOLD JOHN C·Filed 2012·Granted Dec 23, 2014·21 cites·25 claims
- 2995US8896067B2Method of forming finFET of variable channel widthIBM·Filed 2013·Granted Nov 25, 2014·20 cites·13 claims
- 3095US6506660B2Semiconductor with nanoscale featuresIBM·Filed 2001·Granted Jan 14, 2003·101 cites·18 claims
- 3195US6387783B1Methods of T-gate fabrication using a hybrid resistIBM·Filed 1999·Granted May 14, 2002·134 cites·18 claims
- 3295US6096598AMethod for forming pillar memory cells and device formed therebyIBM·Filed 1998·Granted Aug 1, 2000·200 cites·23 claims
- 3395US5945707ADRAM cell with grooved transfer deviceIBM·Filed 1998·Granted Aug 31, 1999·127 cites·15 claims
- 3494US9263290B2Sub-lithographic semiconductor structures with non-constant pitchGLOBALFOUNDRIES INC·Filed 2015·Granted Feb 16, 2016·8 cites·7 claims
- 3594US9147576B2Gate contact with vertical isolation from source-drainIBM·Filed 2014·Granted Sep 29, 2015·12 cites·17 claims
- 3694US8525339B2Hybrid copper interconnect structure and method of fabricating sameYANG CHIH-CHAO·Filed 2011·Granted Sep 3, 2013·16 cites·16 claims
- 3794US8383490B2Borderless contact for ultra-thin body devicesIBM·Filed 2011·Granted Feb 26, 2013·15 cites·10 claims
- 3894US7691720B2Vertical nanotube semiconductor device structures and methods of forming the sameIBM·Filed 2007·Granted Apr 6, 2010·22 cites·17 claims
- 3994US7607455B2Micro-electro-mechanical valves and pumps and methods of fabricating sameIBM·Filed 2008·Granted Oct 27, 2009·21 cites·39 claims
- 4094US7535016B2Vertical carbon nanotube transistor integrationIBM·Filed 2005·Granted May 19, 2009·33 cites·20 claims
- 4194US7473633B2Method for making integrated circuit chip having carbon nanotube composite interconnection viasIBM·Filed 2006·Granted Jan 6, 2009·29 cites·18 claims
- 4294US7265013B2Sidewall image transfer (SIT) technologiesIBM·Filed 2005·Granted Sep 4, 2007·25 cites·30 claims
- 4394US7071047B1Method of forming buried isolation regions in semiconductor substrates and semiconductor devices with buried isolation regionsIBM·Filed 2005·Granted Jul 4, 2006·19 cites·34 claims
- 4493US9105693B2Microelectronic structure including air gapEDELSTEIN DANIEL C·Filed 2012·Granted Aug 11, 2015·11 cites·8 claims
- 4593US8941156B2Self-aligned dielectric isolation for FinFET devicesIBM·Filed 2013·Granted Jan 27, 2015·13 cites·16 claims
- 4693US8227339B2Creation of vias and trenches with different depthsPONOTH SHOM·Filed 2009·Granted Jul 24, 2012·17 cites·15 claims
- 4793US7483285B2Memory devices using carbon nanotube (CNT) technologiesIBM·Filed 2008·Granted Jan 27, 2009·27 cites·14 claims
- 4893US7358120B2Silicon-on-insulator (SOI) read only memory (ROM) array and method of making a SOI ROMIBM·Filed 2007·Granted Apr 15, 2008·25 cites·22 claims
- 4993US6891235B1FET with T-shaped gateIBM·Filed 2000·Granted May 10, 2005·56 cites·20 claims
- 5093US6627477B1Method of assembling a plurality of semiconductor devices having different thicknessIBM·Filed 2000·Granted Sep 30, 2003·68 cites·26 claims
Showing the top 50 of 400 patent records by PatentIndex Score.
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