Inventor

HUI ANGELA T

US104 patents

⚠️ This page may combine multiple inventors who share the name “HUI ANGELA T”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HUI ANGELA T

ADVANCED MICRO DEVICES INC

Method of forming smaller contact size using a spacer hard mask

Spin on polymers for organic memory devices

Method of forming integrated circuit features by oxidation of titanium hard mask

Polymer memory device formed in via opening

Method(s) facilitating formation of memory cell(s) and patterned conductive

Method and system for providing tapered shallow trench isolation structure profile

Low K dielectic etch in high density plasma etcher

Non self-aligned shallow trench isolation process with disposable space to define sub-lithographic poly space

Flash memory with controlled wordline width

Interconnect methodology employing a low dielectric constant etch stop layer

Method of creating a smaller contact using hard mask

Method for forming a semiconductor device with self-aligned contacts using a liner oxide layer

Semiconductor device with self-aligned contacts using a liner oxide layer

Self-aligning vias for semiconductors

Silicon containing material for patterning polymeric memory element

UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL

Memory wordline hard mask

Innovative narrow gate formation for floating gate flash technology

Method of making memory wordline hard mask extension

Sidewall spacer etch process for improved silicide formation

Method for removing anti-reflective coating layer using plasma etch process after contact CMP

Method of making a memory cell with polished insulator layer

Method and system for reducing charge gain and charge loss when using an ARC layer in interlayer dielectric formation

System and method for improving reliability in a semiconductor device

Flash NVROM devices with UV charge immunity

Narrow wide spacer

Organic spin-on anti-reflective coating over inorganic anti-reflective coating

Method of creating narrow trench lines using hard mask

Optical technique to detect etch process termination

Semiconductor device with contacts having a sloped profile

Method for removing anti-reflective coating layer using plasma etch process before contact CMP

Shallow trench isolation filled with thermal oxide

Method to reduce gate-to-local interconnect capacitance using a low dielectric constant material for LDD spacer

Sidewall spacer for protecting tunnel oxide during isolation trench formation in self-aligned flash memory core

Plasma treatment for polymer removal after via etch

SO2 treatment of oxidized CuO for copper sulfide formation of memory element growth

Thinning of trench and line or contact spacing by use of dual layer photoresist

In-situ process for fabricating a semiconductor device with integral removal of antireflection and etch stop layers

Charge gain/charge loss junction leakage prevention for flash technology by using double isolation/capping layer between lightly doped drain and gate

Method for forming high quality multiple thickness oxide layers by reducing descum induced defects

Capping layer

Method for producing a shallow trench isolation filled with thermal oxide

SPANSION LLC

Void free interlayer dielectric

Method and system for tailoring core and periphery cells in a nonvolatile memory

Dual spacer formation in flash memory

System and method for improving mesa width in a semiconductor device

Etch-back process for capping a polymer memory device

Avoiding field oxide gouging in shallow trench isolation (STI) regions

LIN CHUAN

Integrating transistors with different poly-silicon heights on the same die

(unassigned)

Method for forming high quality multiple thickness oxide using high temperature descum