Inventor · disambiguated record
Puneet Harischandra Suvarna
Also filed as: SUVARNA PUNEET · SUVARNA PUNEET H · Suvarna Puneet Harischandra
20 granted patents·1 pending application·386 citations·filing 2016–2019
95Inventor score
Top patents by PatentIndex Score
21 records- 0199US10256158B1Insulated epitaxial structures in nanosheet complementary field effect transistorsGLOBALFOUNDRIES INC·Filed 2017·Granted Apr 9, 2019·68 cites·20 claims
- 0298US10510622B1Vertically stacked complementary-FET device with independent gate controlGLOBALFOUNDRIES INC·Filed 2018·Granted Dec 17, 2019·46 cites·20 claims
- 0398US10236292B1Complementary FETs with wrap around contacts and methods of forming sameGLOBALFOUNDRIES INC·Filed 2018·Granted Mar 19, 2019·33 cites·9 claims
- 0498US10192867B1Complementary FETs with wrap around contacts and method of forming sameGLOBALFOUNDRIES INC·Filed 2018·Granted Jan 29, 2019·134 cites·6 claims
- 0597US10304833B1Method of forming complementary nano-sheet/wire transistor devices with same depth contactsGLOBALFOUNDRIES INC·Filed 2018·Granted May 28, 2019·19 cites·20 claims
- 0695US10418449B2Circuits based on complementary field-effect transistorsGLOBALFOUNDRIES INC·Filed 2018·Granted Sep 17, 2019·14 cites·20 claims
- 0795US10157794B1Integrated circuit structure with stepped epitaxial regionGLOBALFOUNDRIES INC·Filed 2017·Granted Dec 18, 2018·13 cites·14 claims
- 0895US10141414B1Negative capacitance matching in gate electrode structuresGLOBALFOUNDRIES INC·Filed 2017·Granted Nov 27, 2018·12 cites·18 claims
- 0995US10121702B1Methods, apparatus and system for forming source/drain contacts using early trench silicide cutGLOBALFOUNDRIES INC·Filed 2017·Granted Nov 6, 2018·13 cites·20 claims
- 1093US10784171B2Vertically stacked complementary-FET device with independent gate controlGLOBALFOUNDRIES INC·Filed 2019·Granted Sep 22, 2020·7 cites·19 claims
- 1193US10236379B2Vertical FET with self-aligned source/drain regions and gate length based on channel epitaxial growth processGLOBALFOUNDRIES INC·Filed 2017·Granted Mar 19, 2019·10 cites·20 claims
- 1287US10347745B2Methods of forming bottom and top source/drain regions on a vertical transistor deviceGLOBALFOUNDRIES INC·Filed 2016·Granted Jul 9, 2019·5 cites·17 claims
- 1387US10312154B2Method of forming vertical FinFET device having self-aligned contactsGLOBALFOUNDRIES INC·Filed 2017·Granted Jun 4, 2019·4 cites·16 claims
- 1484US9947789B1Vertical transistors stressed from various directionsGLOBALFOUNDRIES INC·Filed 2016·Granted Apr 17, 2018·4 cites·19 claims
- 1580US10497798B2Vertical field effect transistor with self-aligned contactsGLOBALFOUNDRIES INC·Filed 2019·Granted Dec 3, 2019·2 cites·17 claims
- 1672US10332969B2Negative capacitance matching in gate electrode structuresGLOBALFOUNDRIES INC·Filed 2018·Granted Jun 25, 2019·1 cites·20 claims
- 1770US10446659B2Negative capacitance integration through a gate contactGLOBALFOUNDRIES INC·Filed 2017·Granted Oct 15, 2019·1 cites·16 claims
- 1863US11038092B2Fin-based devices based on the thermoelectric effectGLOBALFOUNDRIES US INC·Filed 2019·Granted Jun 15, 2021·0 cites·11 claims
- 1951US10943992B2Transistor having straight bottom spacersIBM·Filed 2019·Granted Mar 9, 2021·0 cites·20 claims
- 2051US2018342661A1Fin-based devices based on the thermoelectric effectGLOBALFOUNDRIES INC·Filed 2017·Application pending·0 cites
- 2142US10170617B2Vertical transport field effect transistorsGLOBALFOUNDRIES INC·Filed 2017·Granted Jan 1, 2019·0 cites·15 claims
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