Inventor
WU CHAU-CHIN
US40 patents
⚠️ This page may combine multiple inventors who share the name “WU CHAU-CHIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEGRATED DEVICE TECH
35 patentsUS6563754B1May 13, 2003
DRAM circuit with separate refresh memory
INTEGRATED DEVICE TECH479 citations99
US6262907B1Jul 17, 2001
Ternary CAM array
INTEGRATED DEVICE TECH84 citations98
US7304875B1Dec 4, 2007
Content addressable memory (CAM) devices that support background BIST and BISR operations and methods of operating same
INTEGRATED DEVICE TECH51 citations96
US6879504B1Apr 12, 2005
Content addressable memory (CAM) devices having error detection and correction control circuits therein and methods of operating same
INTEGRATED DEVICE TECH42 citations96
US6781857B1Aug 24, 2004
Content addressable memory (CAM) devices that utilize multi-port CAM cells and control logic to support multiple overlapping search cycles that are asynchronously timed relative to each other
INTEGRATED DEVICE TECH64 citations96
US6373739B1Apr 16, 2002
Quad CAM cell with minimum cell size
INTEGRATED DEVICE TECH58 citations96
US6256216B1Jul 3, 2001
Cam array with minimum cell size
INTEGRATED DEVICE TECH61 citations96
US6205049B1Mar 20, 2001
Five-transistor SRAM cell
INTEGRATED DEVICE TECH80 citations96
US6128207AOct 3, 2000
Low-power content addressable memory cell
INTEGRATED DEVICE TECH67 citations96
US6037807AMar 14, 2000
Synchronous sense amplifier with temperature and voltage compensated translator
INTEGRATED DEVICE TECH90 citations96
US7359275B1Apr 15, 2008
Reduced size dual-port SRAM cell
INTEGRATED DEVICE TECH35 citations93
US6661687B1Dec 9, 2003
Cam circuit with separate memory and logic operating voltages
INTEGRATED DEVICE TECH29 citations93
US6657878B2Dec 2, 2003
Content addressable memory (CAM) devices having reliable column redundancy characteristics and methods of operating same
INTEGRATED DEVICE TECH42 citations93
US6512685B1Jan 28, 2003
CAM circuit with separate memory and logic operating voltages
INTEGRATED DEVICE TECH20 citations93
US6505271B1Jan 7, 2003
Increasing priority encoder speed using the most significant bit of a priority address
INTEGRATED DEVICE TECH22 citations93
US6470418B1Oct 22, 2002
Pipelining a content addressable memory cell array for low-power operation
INTEGRATED DEVICE TECH32 citations93
US6266263B1Jul 24, 2001
CAM array with minimum cell size
INTEGRATED DEVICE TECH37 citations93
US6724601B2Apr 20, 2004
ESD protection circuit
INTEGRATED DEVICE TECH19 citations92
US6388499B1May 14, 2002
Level-shifting signal buffers that support higher voltage power supplies using lower voltage MOS technology
INTEGRATED DEVICE TECH38 citations92
US6101116AAug 8, 2000
Six transistor content addressable memory cell
INTEGRATED DEVICE TECH34 citations92
US5994945ANov 30, 1999
Circuit for compensating for variations in both temperature and supply voltage
INTEGRATED DEVICE TECH23 citations88
US6215708B1Apr 10, 2001
Charge pump for improving memory cell low VCC performance without increasing gate oxide thickness
INTEGRATED DEVICE TECH15 citations84
US7187571B1Mar 6, 2007
Method and apparatus for CAM with reduced cross-coupling interference
INTEGRATED DEVICE TECH7 citations74
US5341333AAug 23, 1994
Circuits and methods for amplification of electrical signals
INTEGRATED DEVICE TECH11 citations74
US5517131AMay 14, 1996
TTL input buffer with on-chip reference bias regulator and decoupling capacitor
INTEGRATED DEVICE TECH7 citations73
US5483183AJan 9, 1996
Bipolar current sense amplifier
INTEGRATED DEVICE TECH10 citations73
US5376843ADec 27, 1994
TTL input buffer with on-chip reference bias regulator and decoupling capacitor
INTEGRATED DEVICE TECH11 citations73
US7414460B1Aug 19, 2008
System and method for integrated circuit charge recycling
INTEGRATED DEVICE TECH7 citations72
US6859378B1Feb 22, 2005
Multiple match detection logic and gates for content addressable memory (CAM) devices
INTEGRATED DEVICE TECH8 citations72
US7545660B1Jun 9, 2009
Method and apparatus for CAM with reduced cross-coupling interference
INTEGRATED DEVICE TECH2 citations63
US7522438B1Apr 21, 2009
Method and apparatus for CAM with reduced cross-coupling interference
INTEGRATED DEVICE TECH1 citations63
US7248492B1Jul 24, 2007
Method and apparatus for CAM with reduced cross-coupling interference
INTEGRATED DEVICE TECH2 citations63
US5017812AMay 21, 1991
Combined ECL-to-TTL translator and decoder
INTEGRATED DEVICE TECH4 citations63
US6924994B1Aug 2, 2005
Content addressable memory (CAM) devices having scalable multiple match detection circuits therein
INTEGRATED DEVICE TECH4 citations61
USRE39227EAug 8, 2006
Content addressable memory (CAM) arrays and cells having low power requirements
INTEGRATED DEVICE TECH1 citations52
NETLOGIC MICROSYSTEMS INC
2 patentsUSRE41351EMay 25, 2010
CAM arrays having CAM cells therein with match line and low match line connections and methods of operating same
NETLOGIC MICROSYSTEMS INC2 citations63
US7859876B1Dec 28, 2010
Method and apparatus for CAM with reduced cross-coupling interference
NETLOGIC MICROSYSTEMS INC0 citations52