Inventor

GUO JIACEN

US34 patents

⚠️ This page may combine multiple inventors who share the name “GUO JIACEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GUO JIACEN

SANDISK TECHNOLOGIES LLC

Variable bit line bias for nonvolatile memory

Memory cell group read with compensation for different programming speeds

Non-volatile memory with staggered ramp down at the end of pre-charging

Data retention reliability

Three-bit-per-cell programming using a four-bit-per-cell programming algorithm

MLC programming techniques in a memory device

Non-volatile memory with different word line to word line pitches

Read techniques to reduce read errors in a memory device

Two-side staircase pre-charge in sub-block mode of three-tier non-volatile memory architecture

Audit techniques for read disturb detection in an open memory block

Techniques for erasing the memory cells of edge word lines

Systems and methods for adapting sense time

Fast open block erase in non-volatile memory structures

Channel pre-charge process in a memory device

In-place write techniques without erase in a memory device

Hole channel pre-charge to enable large-volume in-place data sanitization of non-volatile memory

Low power multi-level cell (MLC) programming in non-volatile memory structures

Non-volatile memory with early dummy word line ramp down after precharge

High speed multi-level cell (MLC) programming in non-volatile memory structures

Non-volatile memory with suspension period during programming

Non-volatile memory with one sided phased ramp down after program-verify

Non-volatile memory with tier-wise ramp down after program-verify

String or block or die level dependent source line voltage for neighbor drain side select gate interference compensation

Non-volatile memory with zoned control for limiting programming for different groups of non-volatile memory cells

Non-volatile memory with engineered channel gradient

In-place write techniques without erase in a memory device

SANDISK TECHNOLOGIES INC

Temperature compensation for pre-charge spike in multi-pass programming

Non-volatile memory with sub-blocks

Memory program-verify with adaptive sense time based on row location

Programming techniques to improve erase state upper tails in a memory device

Precharge scheme during programming of a memory device

Multi-tier sub-block mode operation

Non-volatile memory with early ramp for improved performance

Non-volatile memory with dummy word line assisted pre-charge