Precharge scheme during programming of a memory device

Abstract

The memory device includes at least one memory block with source and drain sides and a plurality of memory cells arranged in a plurality of word lines. The word lines are arranged in a plurality of independently programmable and erasable sub-blocks. Control circuitry is configured to program the memory cells of a selected sub-block and determine a location of the within the at least one memory block and determine a programming condition of at least one unselected sub-block. The control circuitry is also configured to program at least one word line in the selected sub-block in a plurality of program loops that include pre-charging processes. The control circuitry pre-charges a plurality of channels from either the source or drain side based on at least one of the location of the selected sub-block within the memory block and the programming condition of the at least one unselected sub-block.

What is claimed is: 
     
         1 . A method of programming a memory device, comprising the steps of:
 preparing a memory device that includes at least one memory block, the at least one memory block having a source side and a drain side and including a plurality of memory cells arranged in a plurality of word lines, and the plurality of word lines being arranged in a plurality of sub-blocks that are configured to be programmed and erased independently of one another;   determining a location of a selected sub-block of the plurality of sub-blocks within the at least one memory block and a programming condition of at least one unselected sub-block of the plurality of sub-blocks;   programming at least one word line in the selected sub-block in a plurality of program loops, the program loops including a pre-charging process, and the pre-charging process starts from either the source side or the drain side of the at least one memory block based on at least one of the location of the selected sub-block within the at least one memory block and the programming condition of the at least one unselected sub-block; and   sequentially programming the word lines of the selected sub-block of the plurality of sub- blocks in a direction from the drain side towards the source side regardless of the location of the selected sub-block within the at least one memory block and regardless of the programming condition of the at least one unselected sub-block.   
     
     
         2 . The method of programming the memory device as set forth in  claim 1 , wherein each program loop of the plurality of program loops includes a verify operation that includes applying a pass voltage VREAD to a plurality of unselected word lines in the at least one memory block. 
     
     
         3 . The method of programming the memory device as set forth in  claim 2 , wherein at an end of the verify operation of each program loop, on only one side of a selected word line, at least some of the unselected word lines begin discharging from the pass voltage VREAD one after the other in a direction towards either the source side of the at least one memory block or the drain side of the at least one memory block. 
     
     
         4 . The method of programming the memory device as set forth in  claim 3 , wherein the side of the selected word line that the unselected word lines discharge one after the other is the same side of the selected word line that the pre-charging process starts at. 
     
     
         5 . The method of programming the memory device as set forth in  claim 4 , wherein prior to some of the unselected word lines completing discharging, a pre-charge voltage is applied to at least one of a source line on the source side of the at least one memory block or a bit line on the drain side of the at least one memory block to pre-charge at least one channel in the at least one memory block prior to the completion of the discharging of some of the unselected word lines. 
     
     
         6 . The method of programming the memory device as set forth in  claim 5 , wherein if the selected sub-block is a lower sub-block located on the source side of the at least one memory block, then the pre-charging process starts from the source side of the at least one memory block. 
     
     
         7 . The method of programming the memory device as set forth in  claim 5 , wherein if the selected sub-block is an upper sub-block that is located on the drain side of the at least one memory block and the at least one unselected sub-block is a closed sub-block, then the pre-charging process starts from the drain side of the at least one memory block. 
     
     
         8 . The method of programming the memory device as set forth in  claim 5 , wherein if the selected sub-block is an upper sub-block that is located on the drain side of the at least one memory block and the at least one unselected sub-block is an open sub-block, then the method further includes the steps of:
 determining a number of programmed word lines in the selected sub-block;   comparing the number of programmed word lines in the selected sub-block to a threshold;   if the number of programmed word lines in the selected sub-block is less than the threshold, then the pre-charging process starts from the drain side of the at least one memory block; and   if the number of programmed word lines in the selected sub-block is greater than the threshold, then the pre-charging process starts from the source side of the at least one memory block.   
     
     
         9 . A memory device, comprising:
 at least one memory block, the at least one memory block having a source side and a drain side and including a plurality of memory cells arranged in a plurality of word lines, and the plurality of word lines being arranged in a plurality of sub-blocks that are configured to be programmed and erased independently of one another; and   control circuitry configured to program the memory cells of a selected sub-block of the plurality of sub-blocks, the control circuitry being configured to;
 determine a location of a selected sub-block of the plurality of sub-blocks within the at least one memory block and a programming condition of at least one unselected sub-block of the plurality of sub-blocks, 
 program at least one word line in the selected sub-block in a plurality of program loops, the program loops including pre-charging processes, and wherein the control circuitry pre-charges a plurality of channels in the at least one memory block from either the source side or the drain side of the at least one memory block based on at least one of the location of the selected sub-block within the at least one memory block and the programming condition of the at least one unselected sub-block, and 
 sequentially program the word lines of the selected sub-block of the plurality of sub-blocks in a direction from the drain side towards the source side of the at least one memory block regardless of the location of the selected sub-block within the at least one memory block and regardless of the programming condition of the at least one unselected sub-block. 
   
     
     
         10 . The memory device as set forth in  claim 9 , wherein each program loop of the plurality of program loops includes a verify operation that includes the control circuitry applying a pass voltage VREAD to a plurality of unselected word lines in the at least one memory block. 
     
     
         11 . The memory device as set forth in  claim 10 , wherein at an end of the verify operation of each program loop, on only one side of a selected word line, the control circuitry begins discharging at least some of the unselected word lines from the pass voltage VREAD one after the other in a direction towards either the source side of the at least one memory block or the drain side of the at least one memory block. 
     
     
         12 . The memory device as set forth in  claim 11 , wherein the side that the unselected word lines begin discharging from the pass voltage VREAD one after another is the same side of the selected word line that the control circuitry pre-charges the plurality of channels from. 
     
     
         13 . The memory device as set forth in  claim 12 , wherein prior to some of the unselected word lines completing discharging, the control circuitry applies a pre-charge voltage to at least one of a source line on the source side of the at least one memory block or a bit line on the drain side of the at least one memory block to pre-charge at least one channel in the at least one memory block prior to the completion of the discharge process. 
     
     
         14 . The memory device as set forth in  claim 13 , wherein if the selected sub-block is a lower sub-block located on the source side of the at least one memory block, then the control circuitry starts the pre-charging process from the source side of the at least one memory block. 
     
     
         15 . The memory device as set forth in  claim 13 , wherein if the selected sub-block is an upper sub-block that is located on the drain side of the at least one memory block and the at least one unselected sub-block is a closed sub-block, then the control circuitry starts the pre-charging process from the drain side of the at least one memory block. 
     
     
         16 . The memory device as set forth in  claim 13 , wherein if the selected sub-block is an upper sub-block that is located on the drain side of the at least one memory block and the at least one unselected sub-block is an open sub-block, then the control circuitry is further configured to:
 determine a number of programmed word lines in the selected sub-block;   compare the number of programmed word lines in the selected sub-block to a threshold;   if the number of programmed word lines in the selected sub-block is less than the threshold, then the control circuitry pre-charges the plurality of channels from the drain side of the at least one memory block; and   if the number of programmed word lines in the selected sub-block is greater than the threshold, then the control circuitry pre-charges the plurality of channels from the source side of the at least one memory block.   
     
     
         17 . An apparatus, comprising:
 at least one memory block, the at least one memory block having a source side and a drain side and including a plurality of memory cells arranged in a plurality of word lines, and the plurality of word lines being arranged in a plurality of sub-blocks that are configured to be programmed and erased independently of one another; and   a programming means for programming the memory cells of the at least one memory block to include at least three bits of data per memory cell, when programming a selected sub-block of the plurality of sub-blocks, the programming means being configured to;
 determine a location of a selected sub-block of the plurality of sub-blocks within the at least one memory block and determine a programming condition of at least one unselected sub-block of the plurality of sub-blocks, 
 program a selected word line in the selected sub-block in a plurality of program loops, the program loops including programming pulses and verify operations, 
 during each of the verify operations, apply a pass voltage VREAD to a plurality of unselected word lines, 
 begin discharging the unselected word lines on one side of a selected word line one after the other to remove electrons from a plurality of channels of the at least one memory block on one side of the selected word line, and 
 sequentially program the word lines of the selected sub-block of the plurality of sub-blocks in a direction from the drain side towards the source side of the at least one memory block regardless of the location of the selected sub-block within the memory block and regardless of the programming condition of the at least one unselected sub-block. 
   
     
     
         18 . The apparatus as set forth in  claim 17 , wherein the programming means is further configured to pre-charge the plurality of channels of the at least one memory block from the side of the selected word line that the programming means discharges the unselected word lines one after the other.