Non-volatile memory with one sided phased ramp down after program-verify

Abstract

In a non-volatile memory system that performs programming of selected memory cells (in coordination with pre-charging and boosting of channels for unselected memory cells) and program-verify to determine whether the programming was successful, the system transitions from program-verify to the next dose of programming by concurrently lowering a voltage applied to a selected word line and voltages applied to word lines on a first side of the selected word line at the conclusion of program-verify. Subsequent to lowering the voltage applied to the selected word line, the system successively lowers voltages applied to groups of one or more word lines on a second side of the selected word line at the conclusion of program-verify beginning with a group of one or more word lines immediately adjacent the selected word line and progressing to other groups of one or more word lines disposed increasingly remote from the selected word line.

What is claimed is: 
     
       1. A non-volatile storage apparatus, comprising:
 a plurality of word lines; 
 a plurality of non-volatile memory cells each connected to one of the plurality of word lines; and 
 a control circuit connected to the word lines and the memory cells, the control circuit is configured to lower word line voltages by:
 concurrently lowering a voltage applied to a selected word line and voltages applied to word lines on a first side of the selected word line at a conclusion of a program-verify portion of a program loop of a program operation that comprises multiple program loops, and 
 subsequent to lowering the voltage applied to the selected word line, successively lowering voltages applied to groups of one or more word lines on a second side of the selected word line at the conclusion of the program-verify portion of the program loop of the program operation beginning with a group of one or more word lines immediately adjacent the selected word line and progressing to other groups of one or more word lines disposed increasingly remote from the selected word line. 
 
 
     
     
       2. The non-volatile storage apparatus of  claim 1 , wherein:
 the control circuit configured to concurrently lower the voltage applied to the selected word line and voltages applied to word lines on the first side of the selected word line by lowering the selected word line from a voltage used for program-verify to a lower voltage and lower to word lines on the first side of the selected word line from overdrive voltages to lower voltages; and 
 the control circuit configured to successively lower voltages applied to groups of one or more word lines on the second side of the selected word line by successively lowering the groups of one or more word lines on the second side of the selected word line from overdrive voltages to lower voltages. 
 
     
     
       3. The non-volatile storage apparatus of  claim 1 , wherein:
 the control circuit configured to concurrently lower the voltage applied to the selected word line and voltages applied to word lines on the first side of the selected word line by lowering the selected word line from a verify compare voltage to ground and lowering word lines on the first side of the selected word line from overdrive voltages to ground; and 
 the control circuit configured to successively lower voltages applied to groups of one or more word lines on the second side of the selected word line by successively lowering the groups of one or more word lines on the second side of the selected word line from overdrive voltages to ground. 
 
     
     
       4. The non-volatile storage apparatus of  claim 1 , wherein:
 groups of one or more word lines on the second side of the selected word line each include at least five word lines. 
 
     
     
       5. The non-volatile storage apparatus of  claim 1 , wherein:
 the groups of one or more word lines on the second side of the selected word line include three groups of five word lines and one group comprising all remaining word lines not yet lowered; and 
 the one group comprising all remaining word lines not yet lowered is a group most remote from the selected word line. 
 
     
     
       6. The non-volatile storage apparatus of  claim 1 , wherein:
 the plurality of non-volatile memory cells are arranged as NAND strings to form a block having three sub-blocks, each NAND string includes memory cells in each of the three sub-blocks; and 
 the selected word line is connected to memory cells in one sub-block. 
 
     
     
       7. The non-volatile storage apparatus of  claim 1 , wherein:
 the plurality of non-volatile memory cells are arranged as NAND strings to form a block having three sub-blocks, each NAND string includes memory cells in each of the three sub-blocks; 
 the three sub-blocks include a top sub-block, middle sub-block and bottom sub-block; 
 the selected word line is connected to memory cells only in the middle sub-block; and 
 the control circuit is configured to perform the concurrently lowering of the voltage applied to the selected word line and voltages applied to word lines on the first side of the selected word line and successively lowering voltages applied to groups of one or more word lines on the second side of the selected word line at the conclusion of the program-verify portion of the program loop when memory cells of the top sub-block and the bottom sub-block are programmed. 
 
     
     
       8. The non-volatile storage apparatus of  claim 1 , wherein:
 the plurality of non-volatile memory cells are arranged as NAND strings to form a block having three sub-blocks, each NAND string includes memory cells in each of the three sub-blocks; 
 the three sub-blocks include a top sub-block at a top end of the NAND strings, a bottom sub-block at a bottom end of the NAND strings and middle sub-block between the top sub-block and the bottom sub-block; and 
 the selected word line is connected to memory cells only in the middle sub-block; and 
 the control circuit is configured to pre-charge unselected NAND strings from the bottom end of the unselected NAND strings when programming memory cells in the bottom sub-block. 
 
     
     
       9. The non-volatile storage apparatus of  claim 1 , wherein:
 the plurality of non-volatile memory cells are arranged as NAND strings to form a block having three sub-blocks, each NAND string includes memory cells in each of the three sub-blocks; and 
 the three sub-blocks include a top sub-block at a top end of the NAND strings, a bottom sub-block at a bottom end of the NAND strings and middle sub-block between the top sub-block and the bottom sub-block. 
 
     
     
       10. The non-volatile storage apparatus of  claim 1 , wherein:
 the control circuit is configured to applying doses of programming to the selected word line to program at least a subset of memory cells connected to the selected word line; 
 the control circuit is configured to perform program-verify between the doses of programming; 
 the control circuit configured to perform the lowering of word line voltages at the conclusion of the program-verify between the doses of programming. 
 
     
     
       11. The non-volatile storage apparatus of  claim 10 , wherein:
 the plurality of non-volatile memory cells are arranged as NAND strings; 
 the control circuit is configured to select a first subset of the NAND strings for programming and inhibit a second subset of the NAND strings from programming; and 
 the control circuit configured to perform the lowering of word line voltages such that channel potential of the second subset of NAND strings is at the positive pre-charge voltage at a conclusion of the lowering of word lines voltages. 
 
     
     
       12. The non-volatile storage apparatus of  claim 1 , further comprising:
 a plurality of bit lines, the plurality of non-volatile memory cells are arranged as NAND strings, the bit lines are connected to the NAND strings and the control circuit; 
 a source line connected to the NAND strings and the control circuit; and 
 the control circuit is configured to apply one or more voltages to the source line and the bit lines while performing the lowering of word lines voltages. 
 
     
     
       13. The non-volatile storage apparatus of  claim 1 , further comprising:
 a plurality of bit lines, the plurality of non-volatile memory cells are arranged as NAND strings to form a block having three sub-blocks, each NAND string includes memory cells in each of the three sub-blocks, the three sub-blocks include a top sub-block at a top end of the NAND strings and a bottom sub-block at a bottom end of the NAND strings as well as a middle sub-block between the top sub-block and the bottom sub-block, the bit lines are connected to the NAND strings on the first side of the selected word line and the control circuit; 
 a source line connected to the NAND strings on the first side of the selected word line and the control circuit. 
 
     
     
       14. A method, comprising:
 applying doses of programming to a selected word line of a plurality of word lines connected to multiple NAND strings, a first subset of the NAND strings are selected for programming, a second subset of the NAND strings are not selected for programming, the NAND strings form a block having three sub-blocks, each NAND string includes memory cells in each of the three sub-blocks, the selected word line is connected to multiple memory cells of the NAND strings in a same sub-block; 
 inhibiting the second subset of NAND strings from programming by boosting channels of the second subset of NAND strings from a positive pre-charge voltage to a boosted voltage; and 
 performing program-verify between one pair of successive doses of programming, comprising:
 applying verify signals to the word lines to determine whether at least a subset of the memory cells connected to the selected word line have reached their programming target, and 
 lowering voltages applied to the word lines from the verify signals to one or more reduced voltages at a conclusion of program-verify between one pair of successive doses of programming such that channel potential of the second subset of NAND strings is at the positive pre-charge voltage at a conclusion of the lowering voltages by successively lowering voltages applied to groups of one or more word lines on one side of the selected word line at the conclusion of the program-verify. 
 
 
     
     
       15. The method of  claim 14 , wherein the lowering voltages comprises:
 concurrently lowering the selected word line and unselected word lines on a first side of the selected word line; and 
 after lowering the selected word line, successively lowering voltages applied to groups of one or more unselected word lines on a second side of the selected word line from beginning with a first group of one or more unselected word lines immediately adjacent the selected word line and progressing to other groups of one or more unselected word lines disposed increasingly remote from the selected word line. 
 
     
     
       16. The method of  claim 14 , wherein:
 pre-charging at least a subset of the NAND strings from the one side of the selected word line. 
 
     
     
       17. The method of  claim 14 , wherein:
 the applying doses of programming to a selected word line comprises applying voltage pulses to the selected word line; 
 the applying verify signals to the word lines comprises applying a verify compare voltage to the selected word line and overdrive voltages to unselected word lines; and 
 the lowering voltages comprises:
 concurrently lowering the selected word line from the verify compare voltage to ground and lowering unselected word lines on a source side of the selected word line from the overdrive voltages to ground, and 
 after lowering the selected word line, successively lowering voltages applied to groups of one or more unselected word lines on a drain side of the selected word line from overdrive voltages to ground beginning with a first group of one or more unselected word lines immediately adjacent the selected word line and progressing to other groups of one or more unselected word lines disposed increasingly remote from the selected word line. 
 
 
     
     
       18. The method of  claim 17 , wherein:
 the groups of one or more unselected word lines each include at least five word lines. 
 
     
     
       19. The method of  claim 17 , wherein:
 the groups of one or more unselected word lines includes two groups of five word lines and one group comprising all remaining word lines not yet lowered; and 
 the one group comprising all remaining word lines not yet lowered is a group most remote from the selected word line. 
 
     
     
       20. A non-volatile storage apparatus, comprising:
 a plurality of non-volatile memory cells arranged as NAND strings to form a block having three sub-blocks, each NAND string includes memory cells in each of the three sub-blocks; 
 a plurality of word lines connected to the NAND strings; 
 a plurality of bit lines connected to the NAND strings; 
 one or more source lines connected to the NAND strings; and 
 means, connected to the word lines and bit lines as well as the one or more source lines, for programming memory cells connected to a selected word line by applying a series of program voltage pulses to the selected word line and performing program-verify between the program voltage pulses, the means for programming concludes program-verify by:
 concurrently lowering a voltage applied to a selected word line from a verify voltage to ground and lowering voltages applied to word lines on a first side of the selected word line from one or more overdrive voltages to ground at a conclusion of program-verify between the program voltage pulses and prior to a next program voltage pulse, and 
 subsequent to lowering the voltage applied to the selected word line, successively lowering voltages applied to groups of one or more word lines on a second side of the selected word line from one or more overdrive voltages to ground at the conclusion of the program-verify between the program voltage pulses beginning with a group of one or more word lines immediately adjacent the selected word line and progressing to other groups of one or more word lines disposed increasingly remote from the selected word line.