Inventor

ARIMOTO KAZUTAMI

JP200 patents

⚠️ This page may combine multiple inventors who share the name “ARIMOTO KAZUTAMI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ARIMOTO KAZUTAMI

MITSUBISHI ELECTRIC CORP

Dynamic semiconductor memory device capable of rearranging data storage from a one bit/one cell scheme in a normal mode to a one bit/two cell scheme in a twin-cell mode for lengthening a refresh interval

Switched backgate bias for FET

Dynamic semiconductor memory device

Semiconductor memory device

CMOS substrate biasing for threshold voltage control

Semiconductor integrated circuit device having hierarchical power source arrangement

Sense amplifier including MOS transistors having threshold voltages controlled dynamically in a semiconductor memory device

Switched substrate bias for logic circuits

Dynamic semiconductor memory device of a twisted bit line system having improved reliability of readout

Semiconductor chip scale package and ball grid array structures

Dynamic semiconductor memory device superior in refresh characteristics

Semiconductor memory device suitable for merging with logic

Memory-embedded semiconductor integrated circuit device having low power consumption

Word line non-boosted dynamic semiconductor memory device

Multi-bank clock synchronous type semiconductor memory device having improved memory array and power supply arrangement

Random access memory with a plurality amplifier groups for reading and writing in normal and test modes

Semiconductor memory device supporting cache and method of driving the same

Switched substrate bias for MOS-DRAM circuits

Semiconductor integrated circuit device having hierarchical power source arrangement

Semiconductor memory device capable of reliably performing burn-in test at wafer level

Semiconductor integrated circuit

Semiconductor integrated circuit device capable of performing operational test for contained memory core at operating frequency higher than that of memory tester

Semiconductor memory device performing redundancy repair based on operation test and semiconductor integrated circuit device having the same

CMOS semiconductor device

Semiconductor integrated circuit device having hierarchical power source arrangement

Semiconductor integrated circuit device having hierarchical power source arrangement

Semiconductor memory device capable of increasing chip yields while maintaining rapid operation

Semiconductor integrated circuit device in which influence of power supply noise on internal circuitry during operation of input/output buffer is prevented

Column selecting circuit in semiconductor memory device

Switched substrate bias for MOS DRAM circuits

Arrangement of power supply and data input/output pads in semiconductor memory device

Dynamic semiconductor memory device with SOI structure and body refresh circuitry

Semiconductor memory device with reduced current consumption in data holding mode

Semiconductor memory device

Semiconductor memory device with an improved hierarchical power supply line configuration

Dynamic semiconductor memory device having excellent charge retention characteristics

Arrangement of power supply and data input/output pads in semiconductor memory device

Semiconductor memory device having self-refreshing function

Circuitry and method for clamping a boost signal

Semiconductor memory device having power line arranged in a meshed shape

Layout of a semiconductor memory device

Semiconductor device incorporating internal voltage down converting circuit

Dynamic random access memory having stacked capacitor structure

Dynamic type semiconductor memory device having an error checking and correcting circuit

Charge-transfer sense amplifier for dram and operating method therefor

RENESAS TECH CORP

Semiconductor device and semiconductor signal processing apparatus

Semiconductor device and semiconductor signal processing apparatus

Refresh-free dynamic semiconductor memory device

Semiconductor memory device having a memory cell structure of reduced occupying area

SHIMANO HIROKI

Semiconductor signal processing device