Inventor

DAMODARAN RAGURAM

US62 patents

⚠️ This page may combine multiple inventors who share the name “DAMODARAN RAGURAM”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DAMODARAN RAGURAM

TEXAS INSTRUMENTS INC

Hub interface unit and application unit interfaces for expanded direct memory access processor

Performance and power improvement on DMA writes to level two combined cache/SRAM that is cached in level one data cache and line is valid and dirty

Programmable built in self test of memory

Lookahead priority collection to support priority elevation

Level one data cache line lock and enhanced snoop protocol during cache victims and writebacks to maintain level one data cache and level two cache coherence

Zero cycle clock invalidate operation

Memory error detection reporting

Process parameter based I/O timing programmability using electrical fuse elements

Programmable address-based write-through cache control

Lookahead priority collection to support priority elevation

Lookahead priority collection to support priority elevation

Parallel processing of multiple block coherence operations

Integer and half clock step division digital variable clock divider

Process parameter based I/O timing programmability using electrical fuse elements

Emulation cache access for tag view reads

Unique pBIST features for advanced memory testing

ROM-based memory testing

Hardware configurable hub interface unit

Zero cycle clock invalidate operation

Process variability tolerant programmable memory controller for a pipelined memory system

Distributed power control for controlling power consumption based on detected activity of logic blocks

Multiple pBIST controllers

DAMODARAN RAGURAM

Requester based transaction status reporting in a system with multi-level memory

Memory attribute sharing between differing cache levels of multilevel cache

Optimizing tag forwarding in a two level cache system from level one to lever two controllers for cache coherence protocol for direct memory access transfers

Programmable address-based write-through cache control

Level one data cache line lock and enhanced snoop protocol during cache victims and writebacks to maintain level one data cache and level two cache coherence

Distributed user controlled multilevel block and global cache coherence with accurate completion status

Managing bandwidth allocation in a processing node using distributed arbitration

Asynchronous clock dividers to reduce on-chip variations of clock timing

At speed testing of high performance memories with a multi-port BIS engine

QUALCOMM INC

Storing narrow produced values for instruction operands directly in a register map in an out-of-order processor

Selective storing of previously decoded instructions of frequently-called instruction sequences in an instruction sequence buffer to be executed by a processor

Multiple instruction issuance with parallel inter-group and intra-group picking

Providing load address predictions using address prediction tables based on load path history in processor-based systems

Dynamic pipeline throttling using confidence-based weighting of in-flight branch instructions

Speculative history forwarding in overriding branch predictors, and related circuits, methods, and computer-readable media

Method and apparatus for dynamic clock and voltage scaling in a computer processor based on program phase

Method and apparatus for dynamic clock and voltage scaling in a computer processor based on program phase

CHACHAD ABHIJEET ASHOK

Non-blocking, pipelined write allocates with allocate data merging in a multi-level cache system

Cache with multiple access pipelines

Enhanced pipelining and multi-buffer architecture for level two cache controller to minimize hazard stalls and optimize performance

Hazard prevention for data conflicts between level one data cache line allocates and snoop writes

Process variability tolerant programmable memory controller for a pipelined memory system

TRAN JONATHAN SON HUNG

Configurable source based/requestor based error detection and correction for soft errors in multi-level cache memory to minimize CPU interrupt service routines

Performance and power improvement on DMA writes to level two combined cache/SRAM that is caused in level one data cache and line is valid and dirty

ANDERSON TIMOTHY DAVID

Entry/exit control to/from a low power state in a complex multi level memory system

ZBICIAK JOSEPH RAYMOND MICHAEL

Priority based exception mechanism for multi-level cache controller

BALASUBRAMANIAN DHEERA

Transaction info bypass for nodes coupled to an interconnect fabric

VENKATASUBRAMANIAN RAMAKRISHNAN

Integer and half clock step division digital variable clock divider