Inventor

TSAI CHENG-HSIUNG

TW92 patents

⚠️ This page may combine multiple inventors who share the name “TSAI CHENG-HSIUNG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TSAI CHENG-HSIUNG

TAIWAN SEMICONDUCTOR MFG CO LTD

Method of spacer patterning to form a target integrated circuit pattern

Lithography using high selectivity spacers for pitch reduction

Interconnect structure having an etch stop layer over conductive lines

Self-aligned via structures with barrier layers

Interconnect structure having an etch stop layer over conductive lines

Lithography using high selectivity spacers for pitch reduction

Self-aligned double spacer patterning process

Interconnect structure having an etch stop layer over conductive lines

Integrated circuit interconnects and methods of making same

Integrated circuit interconnects and methods of making same

Method of forming an interconnect structure for a semiconductor device

Interconnect structure having a barrier layer along the sidewall of self-aligned via structures

Method of fabricating self-aligned via structures

Method of forming an interconnect structure for a semiconductor device

Self-aligned double spacer patterning process

Semiconductor device structure and methods of forming the same

Spacer etching process for integrated circuit design

Spacer etching process for integrated circuit design

APPLIED MATERIALS INC

Deposition ring for physical vapor deposition chamber

Detachable electrostatic chuck for supporting a substrate in a process chamber

Base plate for a processing chamber substrate support

Substrate support with multilevel heat transfer mechanism

Deposition ring for physical vapor deposition chamber

Detachable electrostatic chuck for supporting a substrate in a process chamber

Detachable electrostatic chuck

Pedestal assembly with enhanced thermal conductivity

Substrate support with multiple heating zones

High conductance process kit

In situ plasma clean for removal of residue from pedestal surface without breaking vacuum

Methods and apparatus for shutter disk assembly detection

Process kit design for in-chamber heater and wafer rotating mechanism

Substrate position calibration for substrate supports in substrate processing systems

Pad design for electrostatic chuck surface

Apparatus and method for reducing substrate sliding in process chambers

Apparatus to improve substrate temperature uniformity

TAIWAN SEMICONDUCTOR MFG

Spacer etching process for integrated circuit design

Lithography using high selectivity spacers for pitch reduction

Self-aligned double spacer patterning process

Semiconductor patterning

Interconnect structure and method of forming the same

Method for integrated circuit patterning

Self-aligned double spacer patterning process

Semiconductor device manufacturing methods

Method of fabricating an air gap using a damascene process and structure of same

Air-gap formation in interconnect structures

Integrated circuit device having a copper interconnect

Method of semiconducotr integrated circuit fabrication

SANSONI STEVEN V

Electrostatic chuck assembly

ZHU MINGWEI

PVD buffer layers for LED fabrication

GREEN RICHARD J

In situ plasma clean for removal of residue from pedestal surface without breaking vacuum