Inventor

CHI HEEJO

KR85 patents

⚠️ This page may combine multiple inventors who share the name “CHI HEEJO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHI HEEJO

STATS CHIPPAC LTD

Semiconductor device and method of forming 3D dual side die embedded build-up semiconductor package

Integrated circuit packaging system with multi-tier conductive interconnects and method of manufacture thereof

Integrated circuit packaging system with stacked integrated circuit and heat spreader with openings and method of manufacture thereof

Semiconductor device and method of forming interposer frame electrically connected to embedded semiconductor die

Semiconductor device and method of forming conductive posts and heat sink over semiconductor die using leadframe

Integrated circuit packaging system with package-on-package and method of manufacture thereof

Integrated circuit packaging system with a tiered substrate package and method of manufacture thereof

Semiconductor device and method of forming prefabricated multi-die leadframe for electrical interconnect of stacked semiconductor die

Semiconductor device and method of forming RDL and vertical interconnect by laser direct structuring

Semiconductor device and method of forming interposer frame electrically connected to embedded semiconductor die

Semiconductor device and method of forming 3D dual side die embedded build-up semiconductor package

Methods of forming conductive and insulating layers

Semiconductor device and method of forming open cavity in TSV interposer to contain semiconductor die in WLCSMP

Semiconductor device and method of forming conductive posts and heat sink over semiconductor die using leadframe

Semiconductor device and method of forming shielding layer after encapsulation and grounded through interconnect structure

Semiconductor device and method of bonding semiconductor die to substrate in reconstituted wafer form

Semiconductor device and method of forming prefabricated multi-die leadframe for electrical interconnect of stacked semiconductor die

Methods of manufacturing flip chip semiconductor packages using double-sided thermal compression bonding

Semiconductor device and method of simultaneous molding and thermalcompression bonding

CHI HEEJO

Semiconductor device and method of using leadframe bodies to form openings through encapsulant for vertical interconnect of semiconductor die

Semiconductor device and method of forming open cavity in TSV interposer to contain semiconductor die in WLCSMP

Method of forming thin profile WLCSP with vertical interconnect over package footprint

Semiconductor device and method of forming ultra thin multi-die face-to-face WLCSP

Semiconductor device and method of forming open cavity in TSV interposer to contain semiconductor die in WLCSMP

Integrated circuit system with recessed through silicon via pads and method of manufacture thereof

Semiconductor device with thin profile WLCSP with vertical interconnect over package footprint

Semiconductor device with thin profile WLCSP with vertical interconnect over package footprint

Integrated circuit packaging system with package-on-package and method of manufacture thereof

Integrated circuit packaging system with encapsulation and method of manufacture thereof

Integrated circuit packaging system with foldable substrate and method of manufacture thereof

Integrated circuit packaging system with through silicon via base and method of manufacture thereof

Integrated circuit package system with embedded die superstructure and method of manufacture thereof

Integrated circuit packaging system with dual side connection and method of manufacture thereof

CHO NAMJU

Integrated circuit packaging system with encapsulated via and method of manufacture thereof

Carrier system with multi-tier conductive posts and method of manufacture thereof

Integrated circuit packaging system with stacking interconnect and method of manufacture thereof

Method of manufacture of integrated circuit packaging system with multi-tier conductive interconnects

Integrated circuit packaging system with intra substrate die and method of manufacture thereof

SHIN HANGIL

Semiconductor device and method of forming pre-molded semiconductor die having bumps embedded in encapsulant

Integrated circuit packaging system with a dual board-on-chip structure and method of manufacture thereof

Semiconductor device and method of forming vertical interconnect in FO-WLCSP using leadframe disposed between semiconductor die

STATS CHIPPAC PTE LTD

Semiconductor device and method of forming 3D dual side die embedded build-up semiconductor package

Integrated circuit packaging system with joint assembly and method of manufacture thereof

Integrated circuit packaging system with interposer support structure mechanism and method of manufacture thereof

CAMACHO ZIGMUND RAMIREZ

Integrated circuit packaging system with photoimagable dielectric-defined trace and method of manufacture thereof

Integrated circuit packaging system with pre-molded leadframe and method of manufacture thereof

PAGAILA REZA A

Semiconductor device and method of forming interposer with opening to contain semiconductor die

JANG KI YOUN

Integrated circuit packaging system with package-on-package and method of manufacture thereof

YOON IN SANG

Integrated circuit packaging system with an interposer substrate and method of manufacture thereof

PARK YEONGLM

Semiconductor device and method of forming 3D semiconductor package with semiconductor die stacked over semiconductor wafer