Inventor

VANKAYALA VIJAYAKRISHNA J

US44 patents

⚠️ This page may combine multiple inventors who share the name “VANKAYALA VIJAYAKRISHNA J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

VANKAYALA VIJAYAKRISHNA J

MICRON TECHNOLOGY INC

Reduced peak self-refresh current in a memory device

Memory device with a signaling mechanism

Memory device with a clocking mechanism

Memory device with a latching mechanism

Pre-decoder circuitry

Divided quad clock-based inter-die clocking in a three-dimensional stacked memory device

Separate inter-die connectors for data and error correction information and related computing systems, methods, and apparatuses

Methods for parity error alert timing interlock and memory devices and systems employing the same

Access command delay using delay locked loop (DLL) circuitry

Separate inter-die connectors for data and error correction information and related systems, methods, and apparatuses

Methods for parity error synchronization and memory devices and systems employing the same

Apparatuses and method for trimming input buffers based on identified mismatches

Memory device with an input signal management mechanism

Apparatuses and methods for sharing transmission vias for memory devices

Apparatuses and methods for sharing transmission vias for memory devices

CRC error alert synchronization

Reduced shifter memory system

Divided quad clock-based inter-die clocking in a three-dimensional stacked memory device

Divided clock transmission in a three-dimensional stacked memory device

Apparatuses and method for trimming input buffers based on identified mismatches

Memory device with a clocking mechanism

Methods of reducing clock domain crossing timing violations, and related devices and systems

Processing multi-cycle commands in memory devices, and related methods, devices, and systems

Reduced peak self-refresh current in a memory device

Memory device with a clocking mechanism

Memory device with an input signal management mechanism

Pre-decoder circuitry

Asymmetric read-write sequence for interconnected dies

Detection circuitry to detect a deck of a memory array

Repeater scheme for inter-die signals in multi-die package

Inter-die signal load reduction technique in multi-die package

Read operations for a memory array and register

Low power area efficient divided clock shifter scheme for high latency designs

Redundant through-silicon vias

Memory device with a signaling mechanism

Apparatuses and methods for command signal delay

Command-in-pipeline counter for a memory device

Reduced shifter memory system

Apparatus with calibration input mechanism and methods for operating the same

LODESTAR LICENSING GROUP LLC

Access command delay using delay locked loop (DLL) circuitry

Access command delay using command delay circuitry

Separate inter-die connectors for data and error correction information and related computing systems, methods, and apparatuses

VANKAYALA VIJAYAKRISHNA J

Apparatuses, integrated circuits, and methods for synchronizing data signals with a command signal

Apparatuses and methods for improved memory operation times