Inventor

SARANGI SHANTANU

US23 patents

⚠️ This page may combine multiple inventors who share the name “SARANGI SHANTANU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SARANGI SHANTANU

NVIDIA CORP

Test partition external input/output interface control for test partitions in a semiconductor

Scan system interface (SSI) module

Leveraging low power states for fault testing of processing cores at runtime

In system test of chips in functional systems

In-system test of chips in functional systems

In system test of chips in functional systems

Controlling test networks of chips using integrated processors

Method and apparatus to access high volume test data over high speed interfaces

Independent test partition clock coordination across multiple test partitions

Leveraging low power states for fault testing of processing cores at runtime

Techniques for testing semiconductor devices

Leveraging low power states for fault testing of processing cores at runtime

Techniques for isolating interfaces while testing semiconductor devices

Asynchronous in-system testing for autonomous systems and applications

Performing testing utilizing staggered clocks

Technique for enabling on-die noise measurement during ate testing and IST

Granular dynamic test systems and methods

Dynamic independent test partition clock

Granular dynamic test systems and methods

Test data transfer in multi-die systems

Method and system for dynamic standard test access (DSTA) for a logic block reuse

In-system testing for autonomous systems and applications

ADVANCED MICRO DEVICES INC

Chip debug during power gating events