Inventor

ZIERAK MICHAEL J

US42 patents

⚠️ This page may combine multiple inventors who share the name “ZIERAK MICHAEL J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ZIERAK MICHAEL J

IBM

Asymmetric junction field effect transistor

Lateral diffusion field effect transistor with asymmetric gate dielectric profile

Tapered gate oxide in LDMOS devices

Wrapped gate junction field effect transistor

Lateral diffusion field effect transistor with a trench field plate

Junction field effect transistor with a hyperabrupt junction

High voltage laterally diffused metal oxide semiconductor

High voltage laterally diffused metal oxide semiconductor

Modifying layout of IC based on function of interconnect and related circuit and design structure

Modulated trigger device

Dendrite growth control circuit

Dendrite growth control circuit

High voltage laterally diffused metal oxide semiconductor

Isolated zener diode, an integrated circuit incorporating multiple instances of the zener diode, a method of forming the zener diode and a design structure for the zener diode

Double gate depletion mode MOSFET

Modulated trigger device

High resistivity substrate final resistance test structure

Dendrite growth control circuit

GLOBALFOUNDRIES US INC

Structure including resistor network for back biasing FET stack

Unlanded thermal dissipation pillar adjacent active contact

Structure providing poly-resistor under shallow trench isolation and above high resistivity polysilicon layer

High-electron-mobility transistor with field plate and sidewall spacers

Electrically programmable fuse over crystalline semiconductor materials

Fuse element for process-induced damage protection structure

Field-effect transistors with a body pedestal

Structure providing poly-resistor under shallow trench isolation and above high resistivity polysilicon layer

Structure including polycrystalline resistor with dopant-including polycrystalline region thereunder

Temperature detection using negative temperature coefficient resistor in GaN setting

Structure including multi-level field plate and method of forming the structure

Semiconductor structure with in-device high resistivity polycrystalline semiconductor element and method

GLOBALFOUNDRIES INC

Semiconductor structure with a dopant implant region having a linearly graded conductivity level and method of forming the structure

Semiconductor structure with a dopant implant region having a linearly graded conductivity level and method of forming the structure

Structures with contact trenches and isolation trenches

Dual shallow trench isolation (STI) structure for field effect transistor (FET)

ANDERSON FREDERICK G

Isolated Zener diode

Asymmetric junction field effect transistor

FEILCHENFELD NATALIE B

Lateral diffusion field effect transistor with drain region self-aligned to gate electrode

Lateral diffusion field effect transistor with drain region self-aligned to gate electrode

BREITWISCH MATTHEW J

Method to tailor location of peak electric field directly underneath an extension spacer for enhanced programmability of a prompt-shift device

Method to tailor location of peak electric field directly underneath an extension spacer for enhanced programmability of a prompt-shift device

CAMPI JOHN B

Double gate depletion mode MOSFET

HERSHBERGER DOUGLAS B

Asymmetric silicon-on-insulator (SOI) junction field effect transistor (JFET) and a method of forming the asymmetrical SOI JFET