US11637173B2ActiveUtilityA1

Structure including polycrystalline resistor with dopant-including polycrystalline region thereunder

57
Assignee: GLOBALFOUNDRIES US INCPriority: Sep 29, 2020Filed: Sep 29, 2020Granted: Apr 25, 2023
Est. expirySep 29, 2040(~14.2 yrs left)· nominal 20-yr term from priority
H10P 32/302H10W 10/181H10W 10/17H10W 10/061H10W 10/014H10P 90/1906H10P 30/208H10P 30/204H10D 87/00H10D 86/80H10D 86/201H10D 1/474C30B 33/04C30B 29/06C30B 1/04H01L 28/24H01L 21/32155H01L 27/1207
57
PatentIndex Score
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Cited by
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References
18
Claims

Abstract

A structure includes a semiconductor substrate, and a polycrystalline resistor region over the semiconductor substrate. The polycrystalline resistor region includes a semiconductor material in a polycrystalline morphology. A dopant-including polycrystalline region is between the polycrystalline resistor region and the semiconductor substrate.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A structure comprising:
 a semiconductor substrate; 
 a polycrystalline resistor region over the semiconductor substrate, the polycrystalline resistor region including a semiconductor material in a polycrystalline morphology; 
 a silicide layer on the polycrystalline resistor region, and including a first portion coupled to a first contact thereon and a second portion coupled to a second contact thereon; and 
 a dopant-including polycrystalline region between the polycrystalline resistor region and the semiconductor substrate, 
 wherein a dopant of the dopant-including polycrystalline region includes a noble gas element. 
 
     
     
       2. The structure of  claim 1 , wherein the dopant-including polycrystalline region contacts an underside of the polycrystalline resistor region. 
     
     
       3. The structure of  claim 1 , further comprising an oxide layer between the polycrystalline resistor region and the dopant-including polycrystalline region. 
     
     
       4. The structure of  claim 3 , wherein the oxide layer is part of a trench isolation arrangement. 
     
     
       5. The structure of  claim 3 , wherein the oxide layer is part of a gate dielectric layer. 
     
     
       6. The structure of  claim 1 , wherein the polycrystalline resistor region includes polysilicon and the semiconductor substrate includes monocrystalline silicon. 
     
     
       7. The structure of  claim 1 , wherein the dopant includes argon (Ar). 
     
     
       8. The structure of  claim 1 , further comprising an active device over the semiconductor substrate, and wherein the active device includes a monocrystalline body and the dopant-including polycrystalline region extends under the active device,
 wherein the active device includes a polycrystalline gate in the same layer as the polycrystalline resistor region. 
 
     
     
       9. The structure of  claim 1 , wherein the semiconductor substrate includes a semiconductor-on-insulator (SOI) substrate including a semiconductor-on-insulator (SOI) layer over a buried insulator layer over a bulk semiconductor substrate, and
 further comprising an active device over the SOI substrate, and wherein the dopant-damage polycrystalline region does not extend under the active device. 
 
     
     
       10. The structure of  claim 1 , further comprising a well region in the semiconductor substrate under the dopant-including polycrystalline region. 
     
     
       11. The structure of  claim 1 , wherein the silicide layer extends continuously horizontally from the first portion to the second portion. 
     
     
       12. The structure of  claim 1 , further comprising a silicide blocking layer horizontally between the first portion of the silicide layer and the second portion of the silicide layer, wherein the silicide layer is discontinuous between the first portion and the second portion. 
     
     
       13. A structure, comprising:
 a semiconductor substrate; 
 a polycrystalline resistor region over a semiconductor substrate, the polycrystalline resistor region including a semiconductor material in a polycrystalline morphology; 
 a silicide layer on the polycrystalline resistor region, and including a first portion coupled to a first contact thereon and a second portion coupled to a second contact thereon; 
 an argon-including polycrystalline region between the polycrystalline resistor region and the semiconductor substrate; and 
 an active device over the semiconductor substrate, wherein the active device includes a monocrystalline body and the argon-including polycrystalline region extends under the active device. 
 
     
     
       14. The structure of  claim 13 , wherein the argon-including polycrystalline region contacts an underside of the polycrystalline resistor region. 
     
     
       15. The structure of  claim 13 , further comprising an oxide layer between the polycrystalline resistor region and the argon-including polycrystalline region, and wherein the oxide layer is part of one of: a trench isolation arrangement, and a gate dielectric layer. 
     
     
       16. The structure of  claim 13 , further comprising a well region in the semiconductor substrate under the argon-including polycrystalline region. 
     
     
       17. A method comprising:
 forming a first dopant including polycrystalline region by forming a first monocrystalline region in a semiconductor substrate and including a noble gas element therein; 
 forming an oxide layer in the semiconductor substrate to create a dopant-including polycrystalline region under the oxide layer; 
 forming a second monocrystalline region in the semiconductor substrate to create a second dopant-including polycrystalline region, 
 wherein one of the oxide layer and second monocrystalline region include the noble gas element; 
 forming a reformed monocrystalline active region from an upper portion of the first dopant-including polycrystalline region, leaving a portion of the first dopant-including polycrystalline region as an isolation layer under the reformed monocrystalline active region; 
 forming an active device over the reformed monocrystalline active region and a polycrystalline resistor over one of the oxide layer and the second dopant-including polycrystalline region, wherein the oxide layer is part of one of a trench isolation arrangement and a gate dielectric layer; 
 forming a silicide layer on the polycrystalline resistor, the silicide layer including a first portion and a second portion; and 
 forming a first contact on the first portion of the silicide layer and a second contact on the second portion of the silicide layer. 
 
     
     
       18. The method of  claim 17 , further comprising removing a nitride cap from over the second dopant-including polycrystalline region, prior to forming the active device.

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