Inventor

WIATR MACIEJ

DE36 patents

⚠️ This page may combine multiple inventors who share the name “WIATR MACIEJ”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WIATR MACIEJ

GLOBALFOUNDRIES INC

Strain engineering in semiconductor devices by using a piezoelectric material

E-fuse design for high-K metal-gate technology

Method for forming a transistor comprising high-k metal gate electrode structures including a polycrystalline semiconductor material and embedded strain-inducing semiconductor alloys

Semiconductor structure including a transistor having stress creating regions and method for the formation thereof

Semiconductor device having a strained semiconductor alloy concentration profile

Semiconductor device with thin-film resistor

Method for creating tensile strain by repeatedly applied stress memorization techniques

Increasing stress transfer efficiency in a transistor by reducing spacer width during the drain/source implantation sequence

Method for creating tensile strain by selectively applying stress memorization techniques to NMOS transistors

Superior integrity of high-k metal gate stacks by preserving a resist material above end caps of gate electrode structures

KRONHOLZ STEPHAN

Reducing silicide resistance in silicon/germanium-containing drain/source regions of transistors

Reduction of defect rates in PFET transistors comprising a Si/Ge semiconductor material formed by epitaxial growth

Strain engineering in semiconductor devices by using a piezoelectric material

Strain enhancement in transistors comprising an embedded strain-inducing semiconductor alloy by corner rounding at the top of the gate electrode

Semiconductor element formed in a crystalline substrate material and comprising an embedded in situ doped semiconductor material

Transistor comprising an embedded semiconductor alloy in drain and source regions extending under the gate electrode

Test structure for controlling the incorporation of semiconductor alloys in transistors comprising high-k metal gate electrode structures

Enhancing deposition uniformity of a channel semiconductor alloy by forming a recess prior to the well implantation

WIATR MACIEJ

SOI device having a substrate diode formed by reduced implantation energy

Buried etch stop layer in trench isolation structures for superior surface planarity in densely packed semiconductor devices

Compensation of operating time-related degradation of operating speed by a constant total die power mode

Method for differential spacer removal by wet chemical etch process and device with differential spacer structure

HOENTSCHEL JAN

Asymmetric transistor devices formed by asymmetric spacers and tilted implantation

Asymmetric transistor devices formed by asymmetric spacers and tilted implantation

KRONHOLZ STEPHAN-DETLEF

Superior integrity of high-k metal gate stacks by preserving a resist material above end caps of gate electrode structures

Reducing defect rate during deposition of a channel semiconductor alloy into an in situ recessed active region

THEES HANS-JUERGEN

Semiconductor devices comprising a channel semiconductor alloy formed with reduced STI topography

MOWRY ANTHONY

Cold temperature control in a semiconductor device

JAVORKA PETER

Differential threshold voltage adjustment in PMOS transistors by differential formation of a channel semiconductor material

ADVANCED MICRO DEVICES INC

Compensation of degradation of performance of semiconductor devices by clock duty cycle adaptation

SCHEIPER THILO

Sacrificial spacer approach for differential source/drain implantation spacers in transistors comprising a high-k metal gate electrode structure

KAMMLER THORSTEN

Leakage control in field effect transistors based on an implantation species introduced locally at the STI edge

TAN CHUNG FOONG

Method of forming transistor with increased gate width

GLOBAL FOUNDRIES INC

Semiconductor fuse with enhanced post-programming resistance

KURZ ANDREAS

Semiconductor fuse with enhanced post-programming resistance

GEHRING ANDREAS

Method for forming silicon/germanium containing drain/source regions in transistors with reduced silicon/germanium loss