Inventor

BOSCHKE ROMAN

DE34 patents

⚠️ This page may combine multiple inventors who share the name “BOSCHKE ROMAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BOSCHKE ROMAN

GLOBALFOUNDRIES INC

E-fuse design for high-K metal-gate technology

Simplified gate-first HKMG manufacturing flow

Semiconductor device structure and methods for forming a CMOS integrated circuit structure

Transistor with embedded Si/Ge material having reduced offset and superior uniformity

Temperature monitoring in a semiconductor device by thermocouples distributed in the contact structure

Blocking pre-amorphization of a gate electrode of a transistor

Silicidation of semiconductor devices

Method for forming a strained transistor by stress memorization based on a stressed implantation mask

Increasing stress transfer efficiency in a transistor by reducing spacer width during the drain/source implantation sequence

Methods for fabricating semiconductor devices

Transistor with embedded silicon/germanium material on a strained semiconductor on insulator substrate

Sandwich silicidation for fully silicided gate formation

KRONHOLZ STEPHAN

Transistor with embedded Si/Ge material having reduced offset and superior uniformity

Reduction of defect rates in PFET transistors comprising a Si/Ge semiconductor material formed by epitaxial growth

Strain enhancement in transistors comprising an embedded strain-inducing semiconductor alloy by corner rounding at the top of the gate electrode

Semiconductor element formed in a crystalline substrate material and comprising an embedded in situ doped semiconductor material

Enhancing deposition uniformity of a channel semiconductor alloy by forming a recess prior to the well implantation

KURZ ANDREAS

SOI device with a buried insulating material having increased etch resistivity

Semiconductor device comprising a buried poly resistor

Semiconductor device comprising a silicon/germanium resistor

ADVANCED MICRO DEVICES INC

Formation of transistor having a strained channel region including a performance enhancing material composition utilizing a mask pattern

Semiconductor device having a high-K gate dielectric above an STI region

WEI ANDY

SOI transistor having drain and source regions of reduced length and a stressed dielectric material adjacent thereto

Method for self-aligned removal of a high-K gate dielectric above an STI region

WIATR MACIEJ

SOI device having a substrate diode formed by reduced implantation energy

Buried etch stop layer in trench isolation structures for superior surface planarity in densely packed semiconductor devices

JAVORKA PETER

Transistor with boot shaped source/drain regions

IMEC VZW

FinFET having locally higher fin-to-fin pitch

WIRBELEIT FRANK

Method for forming a strained transistor by stress memorization based on a stressed implantation mask

KAMMLER THORSTEN

Leakage control in field effect transistors based on an implantation species introduced locally at the STI edge

AUBEL OLIVER

Semiconductor device comprising eFUSES of enhanced programming efficiency

RICHTER RALF

Enhanced transistor performance of N-channel transistors by using an additional layer above a dual stress liner in a semiconductor device

HOENTSCHEL JAN

Stress adjustment in stressed dielectric materials of semiconductor devices by stress relaxation based on radiation

GEHRING ANDREAS

Method for forming silicon/germanium containing drain/source regions in transistors with reduced silicon/germanium loss