Sandwich silicidation for fully silicided gate formation

Abstract

When forming field effect transistors, a common problem is the formation of a Schottky barrier at the interface between a metal thin film in the gate electrode and a semiconductor material, typically polysilicon, formed thereupon. Fully silicided gates are known in the state of the art which may overcome this problem. The claimed method proposes an improved fully silicided gate achieved by forming a gate structure including an additional metal layer between the metal gate layer and the gate semiconductor material. A silicidation process can then be optimized so as to form a lower metal silicide layer comprising the metal of the additional metal layer and an upper metal silicide layer forming an interface with the lower metal silicide layer.

What is claimed: 
     
       1. A method of forming a transistor, the method comprising:
 forming an active region in a semiconductor layer; and 
 forming a gate structure on said active region, wherein forming said gate structure comprises:
 forming an insulating layer on said active region; 
 forming a gate metal layer on said insulating layer, wherein said gate metal layer does not comprise silicon-based or metal silicide materials; 
 forming a first metal layer on said gate metal layer, wherein said first metal layer does not comprise silicon-based or metal silicide materials; 
 forming a gate material layer on said first metal layer; and 
 performing a salicidation process to form a first metal silicide layer above said gate metal layer and to form a second metal silicide layer above said first metal silicide layer, said salicidation process comprising:
 depositing a refractory metal layer above said transistor after forming said gate structure; and 
 applying a heat treatment to form said second metal silicide layer from at least a portion of said refractory metal layer and at least a portion of said gate material layer. 
 
 
 
     
     
       2. The method of  claim 1 , wherein said first metal layer comprises at least one of titanium and cobalt. 
     
     
       3. The method of  claim 1 , wherein forming said gate structure comprises performing a common patterning process on said insulating layer, said gate metal layer, said first metal layer and said gate material layer. 
     
     
       4. The method of  claim 1 , further comprising forming a source region and a drain region of said transistor in said active region, said source and drain regions being formed after forming said gate structure. 
     
     
       5. The method of  claim 1 , wherein forming said first metal silicide layer comprises forming a metal silicide material from at least a portion of said gate material layer and at least a portion of said first metal layer. 
     
     
       6. The method of  claim 1 , wherein said second metal silicide layer comprises nickel silicide. 
     
     
       7. The method of  claim 1 , wherein said salicidation process is performed in a single step after forming said gate structure. 
     
     
       8. The method of  claim 1 , wherein performing said salicidation process comprises forming an interface between said first metal silicide layer and said second metal silicide layer. 
     
     
       9. The method of  claim 1 , wherein performing said salicidation process comprises forming an interface between said first metal silicide layer and said gate metal layer. 
     
     
       10. The method of  claim 1 , wherein said insulating layer of said gate structure comprises a high-k dielectric material. 
     
     
       11. The method of  claim 10 , wherein said high-k dielectric material comprises at least one of tantalum oxide (Ta 2 O 5 ), strontium titanium oxide (SrTiO 3 ), hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO) and zirconium oxide (ZrO 2 ). 
     
     
       12. The method of  claim 1 , wherein said gate metal layer comprises at least one of tantalum (Ta), tungsten (W), titanium nitride (TiN), and tantalum nitride (TaN). 
     
     
       13. A method, comprising:
 forming a gate structure material stack above an active region formed in a layer of semiconductor material, wherein forming said gate structure material stack comprises:
 forming a gate insulation layer above said active region, said gate insulation layer comprising a high-k dielectric material having a dielectric constant that is greater than approximately 10; 
 depositing a metal gate layer above said gate insulation layer, wherein said metal gate layer comprises a work function adjusting metal species but does not comprise silicon-based or metal silicide materials; 
 depositing a first metal layer above said metal gate layer, said first metal layer comprising a first refractory metal; and 
 forming a silicon-based semiconductor layer on and in contact with an upper surface of said first metal layer; 
 
 performing a common gate patterning process on said gate structure material stack to form a gate structure comprising at least said gate insulation layer, said metal gate layer, said first metal layer and said silicon-based semiconductor layer; 
 after forming said gate structure, forming a second metal layer on and in contact with an upper surface of said silicon-based semiconductor layer of said gate structure, said second metal layer comprising a second refractory metal that is different than said first refractory metal; and 
 performing at least one heat treatment process to form a first metal silicide material from at least a portion of said first refractory metal of said first metal layer and a lower portion of said silicon-based semiconductor layer and to form a second metal silicide material from at least a portion of said second refractory metal of said second metal layer and an upper portion of said silicon-based semiconductor layer. 
 
     
     
       14. The method of  claim 13 , wherein, after performing said at least one heat treatment process, said first metal silicide material forms an interface with said second metal silicide material. 
     
     
       15. The method of  claim 13 , wherein, after performing said at least one heat treatment process, said first metal silicide material forms an interface with said metal gate layer. 
     
     
       16. The method of  claim 13 , wherein said first metal silicide material comprises at least one of titanium disilicide (TiSi 2 ) and cobalt disilicide (CoSi 2 ). 
     
     
       17. The method of  claim 13 , wherein said second metal silicide layer comprises nickel silicide (NiSi). 
     
     
       18. The method of  claim 13 , wherein said high-k dielectric material comprises at least one of tantalum oxide (Ta 2 O 5 ), strontium titanium oxide (SrTiO 3 ), hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO) and zirconium oxide (ZrO 2 ). 
     
     
       19. The method of  claim 13 , wherein said metal gate layer comprises at least one of tantalum (Ta), tungsten (W), titanium nitride (TiN), and tantalum nitride (TaN). 
     
     
       20. A method of forming a transistor, the method comprising:
 forming an active region in a semiconductor layer; and 
 forming a gate structure on said active region, wherein forming said gate structure comprises:
 forming an insulating layer on said active region; 
 forming a gate metal layer on said insulating layer, wherein said gate metal layer does not comprise silicon-based or metal silicide materials; 
 forming a first metal layer on said gate metal layer, wherein said first metal layer does not comprise silicon-based or metal silicide materials; 
 forming a gate material layer on said first metal layer; and 
 performing a salicidation process to form a first metal silicide layer above said gate metal layer, a second metal silicide layer above said first metal silicide layer, and a third metal silicide layer in said source and drain regions, said salicidation process comprising:
 depositing a refractory metal layer above said transistor after forming said gate structure; and 
 applying a heat treatment to form said second metal silicide layer from a first portion of said refractory metal layer and at least a portion of said gate material layer and to form said third metal silicide layer from a second portion of said refractory metal layer and a portion of a semiconductor material comprising said source and drain regions. 
 
 
 
     
     
       21. The method of  claim 20 , wherein said third metal silicide layer has substantially a same thickness as said second metal silicide layer. 
     
     
       22. The method of  claim 20 , wherein said first metal layer comprises at least one of titanium (Ti) and cobalt (Co). 
     
     
       23. The method of  claim 20 , wherein said refractory metal layer comprises nickel. 
     
     
       24. The method of  claim 20 , wherein performing said salicidation process comprises forming an interface between said first metal silicide layer and said second metal silicide layer. 
     
     
       25. The method of  claim 20 , wherein performing said salicidation process comprises forming an interface between said first metal silicide layer and said gate metal layer. 
     
     
       26. The method of  claim 20 , wherein said insulating layer of said gate structure comprises a high-k dielectric material. 
     
     
       27. The method of  claim 26 , wherein said high-k dielectric material comprises at least one of tantalum oxide (Ta 2 O 5 ), strontium titanium oxide (SrTiO 3 ), hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO) and zirconium oxide (ZrO 2 ). 
     
     
       28. The method of  claim 20 , wherein said gate metal layer comprises at least one of tantalum (Ta), tungsten (W), titanium nitride (TiN), and tantalum nitride (TaN).