Inventor

ELLIS WAYNE FREDERICK

US35 patents

⚠️ This page may combine multiple inventors who share the name “ELLIS WAYNE FREDERICK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ELLIS WAYNE FREDERICK

RAMBUS INC

High capacity memory systems with inter-rank skew tolerance

Memory component with multiple command/address sampling modes

Memory control component with inter-rank skew tolerance

1T-1R architecture for resistive random access memory

Communication via a memory interface

Multi-element memory device with power control for individual elements

Multi-element memory device with power control for individual elements

Memory control component with dynamic command/address signaling rate

1T-1R architecture for resistive random access memory

Multi-element memory device with power control for individual elements

Memory component timed by programmably-selected clock edge

Multi-element memory device with power for individual elements

Communication via a memory interface

Multi-element memory device with power control for individual elements

HEFEI RELIANCE MEMORY LTD

2T-1R architecture for resistive RAM

1T-1R architecture for resistive random access memory

2T-1R architecture for resistive ram

1T-1R architecture for resistive random access memory

2T-1R architecture for resistive RAM

1T-1R architecture for resistive random access memory

2T-1R architecture for resistive ram

2T-1R architecture for resistive RAM

2T-1R architecture for resistive RAM

IBM

Multi-port multiple-simultaneous-access DRAM chip

System and method for measuring circuit performance degradation due to PFET negative bias temperature instability (NBTI)

Memory device with programmable self-refreshing and testing methods therefore

QIMONDA NORTH AMERICA CORP

Self-diagnostic scheme for detecting errors

Method and apparatus for implementing memory enabled systems using master-slave architecture

Structure to share internally generated voltages between chips in MCP

QIMONDA AG

Memory refresh system and method

Method and apparatus for synchronizing memory enabled systems with master-slave architecture

Method and structure of expanding, upgrading, or fixing multi-chip package

OH JONG HOON

Multi-chip package with interconnected stacked chips

DRESSLER DEBORAH LINDSEY

Multi-element memory device with power control for individual elements

RICHARDSON WAYNE S

Robust commands for timing calibration or recalibration