2T-1R architecture for resistive RAM

Abstract

Provided are a device comprising a bit cell tile including at least two memory cells, each of the at least two memory cells including a resistive memory element, and methods of operating an array of the memory cells, each memory cell including a resistive memory element electrically coupled in series to a corresponding first transistor and to a corresponding second transistor, the first transistor including a first gate coupled to a corresponding one of a plurality of first word lines and the second transistor including a second gate coupled to a corresponding one of a plurality of second word lines, each memory cell coupled between a corresponding one of a plurality of bit lines and a corresponding one of a plurality of source lines. The methods may include applying voltages to the first word line, second word line, source line, and bit line of a memory cell selected for an operation, and resetting the resistive memory element of the memory cell in response to setting the selected bit line to ground.

The invention claimed is: 
     
       1. A method of operating an array of memory cells, each memory cell including a resistive memory element electrically coupled in series to a corresponding first transistor and to a corresponding second transistor, the first transistor including a first gate electrically coupled to a corresponding one of a plurality of first word lines and the second transistor including a second gate electrically coupled to a corresponding one of a plurality of second word lines, each memory cell electrically coupled between a corresponding one of a plurality of bit lines and a corresponding one of a plurality of source lines, the method comprising:
 applying a bit line voltage as a bit line signal to a first bit line electrically coupled to a first memory cell; 
 applying a word line voltage as a word line signal to a first word line electrically coupled to the first transistor of the first memory cell; 
 determining a resistance value for the first memory cell; and 
 responsive to the determined resistance value not reaching a predetermined target resistance value, increasing the word line voltage. 
 
     
     
       2. The method of  claim 1 , further comprising:
 repeating the steps of (i) determining the resistance value for the first memory cell and (ii) responsive to the determined resistance value not reaching the predetermined target resistance value, increasing the word line voltage, until the determined resistance value reaches the predetermined target resistance value. 
 
     
     
       3. The method of  claim 1 , wherein determining the resistance value for the first memory comprises:
 performing a verify read operation on the first memory cell. 
 
     
     
       4. The method of  claim 1 , wherein performing the verify read operation on the first memory cell comprises:
 applying a read bit line voltage as a bit line signal to the bit line of the first memory cell; and 
 applying a read word line signal to the first word line of the first memory cell. 
 
     
     
       5. The method of  claim 1 , wherein the word line voltage as the word line signal is applied to the first word line electrically coupled to the first transistor of the first memory cell through a current limiting selector circuit. 
     
     
       6. The method of  claim 1 , wherein the word line voltage as the word line signal is applied to the first word line electrically coupled to the first transistor of the first memory cell through a unity gain amplifier. 
     
     
       7. The method of  claim 1 , further comprising:
 applying a second word line voltage as a second word line signal to a second word line electrically coupled to the second transistor of the first memory cell prior to determining the resistance value for the first memory cell. 
 
     
     
       8. The method of  claim 7 , wherein:
 the word line voltage as the word line signal is applied to the first word line electrically coupled to the first transistor of the first memory cell through a current limiting selector circuit; and 
 the second word line voltage as the word line signal is applied to the second word line electrically coupled to second first transistor of the first memory cell through the current limiting selector circuit. 
 
     
     
       9. The method of  claim 7 , wherein:
 the word line voltage as the word line signal is applied to the first word line electrically coupled to the first transistor of the first memory cell through a first unity gain amplifier; and 
 the second word line voltage as the word line signal is applied to the second word line electrically coupled to the second transistor of the first memory cell through a second unity gain amplifier. 
 
     
     
       10. The method of  claim 7 , wherein the word line voltage and the second word line voltage are the same. 
     
     
       11. An apparatus comprising:
 an array of memory cells, each memory cell including a resistive memory element electrically coupled in series to a corresponding first transistor and to a corresponding second transistor, the first transistor including a first gate electrically coupled to a corresponding one of a plurality of first word lines and the second transistor including a second gate electrically coupled to a corresponding one of a plurality of second word lines, each memory cell electrically coupled between a corresponding one of a plurality of bit lines and a corresponding one of a plurality of source lines; and 
 a control circuit configured to perform operations comprising: 
 applying a bit line voltage as a bit line signal to a first bit line electrically coupled to a first memory cell; 
 applying a word line voltage as a word line signal to a first word line electrically coupled to the first transistor of the first memory cell; 
 determining a resistance value for the first memory cell; and 
 responsive to the determined resistance value not reaching a predetermined target resistance value, increasing the word line voltage. 
 
     
     
       12. The apparatus of  claim 11 , the operations further comprising:
 repeating the steps of (i) determining the resistance value for the first memory cell and (ii) responsive to the determined resistance value not reaching the predetermined target resistance value, increasing the word line voltage, until the determined resistance value reaches the predetermined target resistance value. 
 
     
     
       13. The apparatus of  claim 11 , wherein determining the resistance value for the first memory comprises:
 performing a verify read operation on the first memory cell. 
 
     
     
       14. The apparatus of  claim 13 , wherein performing the verify read operation on the first memory cell comprises:
 applying a read bit line voltage as a bit line signal to the bit line of the first memory cell; and 
 applying a read word line signal to the first word line of the first memory cell. 
 
     
     
       15. The apparatus of  claim 11 , further comprising:
 a current limiting selector circuit; 
 wherein the word line voltage as the word line signal is applied to the first word line electrically coupled to the first transistor of the first memory cell through the current limiting selector circuit. 
 
     
     
       16. The apparatus of  claim 15 , wherein the current limiting selector circuit comprises:
 a unity gain amplifier configured to apply the word line voltage as the word line signal to the first word line electrically coupled to the first transistor of the first memory cell. 
 
     
     
       17. The apparatus of  claim 11 , the operations further comprising:
 applying a second word line voltage as a second word line signal to a second word line electrically coupled to the second transistor of the first memory cell prior to determining the resistance value for the first memory cell. 
 
     
     
       18. The apparatus of  claim 17 , further comprising:
 a current limiting selector circuit; 
 wherein the word line voltage as the word line signal is applied to the first word line electrically coupled to the first transistor of the first memory cell through the current limiting selector circuit; and 
 wherein the second word line voltage as the word line signal is applied to the second word line electrically coupled to second first transistor of the first memory cell through the current limiting selector circuit. 
 
     
     
       19. The apparatus of  claim 18 , wherein the current limiting selector circuit comprises:
 a first unity gain amplifier configured to apply the word line voltage as the word line signal to the first word line electrically coupled to the first transistor of the first memory cell; and 
 a second unity gain amplifier configured to apply the second word line voltage as the word line signal to the second word line electrically coupled to second first transistor of the first memory cell. 
 
     
     
       20. The apparatus of  claim 17 , wherein the word line voltage and the second word line voltage are the same.