Inventor
GASPARYAN GRIGOR S
US15 patents
Patents
15 patentsUS10783295B1Sep 22, 2020
Netlist partitioning for designs targeting a data processing engine array
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US11238206B1Feb 1, 2022
Partition wire assignment for routing multi-partition circuit designs
XILINX INC14 citations83
US10839121B1Nov 17, 2020
Data processing engine (DPE) array detailed mapping
XILINX INC7 citations83
US10853541B1Dec 1, 2020
Data processing engine (DPE) array global mapping
XILINX INC8 citations79
US10963615B1Mar 30, 2021
Data processing engine (DPE) array routing
XILINX INC3 citations72
US10366201B1Jul 30, 2019
Timing closure of circuit designs for integrated circuits
XILINX INC5 citations72
US10108773B1Oct 23, 2018
Partitioning circuit designs for implementation within multi-die integrated circuits
XILINX INC2 citations71
US10891413B1Jan 12, 2021
Incremental initialization by parent and child placer processes in processing a circuit design
XILINX INC5 citations69
US10108769B1Oct 23, 2018
Delay modeling for high fan-out nets within circuit designs
XILINX INC4 citations69
US11003827B1May 11, 2021
Multiprocessing flow and massively multi-threaded flow for multi-die devices
XILINX INC3 citations66
US9529957B1Dec 27, 2016
Multithreaded scheduling for placement of circuit designs using connectivity and utilization dependencies
XILINX INC2 citations60
US11106851B1Aug 31, 2021
Serialization in electronic design automation flows
XILINX INC0 citations59
US8972920B1Mar 3, 2015
Re-budgeting connections of a circuit design
XILINX INC0 citations49
US10126361B1Nov 13, 2018
Processing of a circuit design for debugging
XILINX INC1 citations47
US8959474B1Feb 17, 2015
Routing multi-fanout nets
XILINX INC0 citations39