Inventor

HOWARD BRADLEY J

US54 patents

⚠️ This page may combine multiple inventors who share the name “HOWARD BRADLEY J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HOWARD BRADLEY J

MICRON TECHNOLOGY INC

Method of forming a capacitor using a photoresist contact sidewall having standing wave ripples

Self-limiting method of reducing contamination in a contact opening, method of making contacts and semiconductor devices therewith, and resulting structures

Formation of a self-aligned integrated circuit structure using silicon-rich nitride as a protective layer

Mask having a tapered profile used during the formation of a semiconductor device

Barrier layer, IC via, and IC line forming methods

Method of plasma etching a substrate

Method of controlling striations and CD loss in contact oxide etch

Method of controlling striations and CD loss in contact oxide etch

Process for using photo-definable layers in the manufacture of semiconductor devices and resulting structures of same

Method of controlling striations and CD loss in contact oxide etch

Apparatus for improving the performance of a temperature-sensitive etch process

Semiconductor processing for forming capacitors by etching polysilicon and coating layer formed over the polysilicon

Process for improving the performance of a temperature-sensitive etch process

Multifrequency plasma reactor

Barrier layer, IC via, and IC line forming methods

Apparatus for improving the performance of a temperature-sensitive etch

Method of removing surface defects or other recesses during the formation of a semiconductor device

Formation of a self-aligned integrated circuit structures using planarization to form a top surface

Method for forming a contact during the formation of a semiconductor device

Method of plasma etching a substrate

Etch aided by electrically shorting upper and lower sidewall portions during the formation of a semiconductor device

Method for manufacturing tapered opening using an anisotropic etch during the formation of a semiconductor device

Plasma etching methods

Mask having a tapered profile used during the formation of a semiconductor device

Recessed-container cells and method of forming the same

Semiconductor processing methods, and methods of forming capacitors

Method of forming an integrated circuit structure

Formation of a self-aligned integrated circuit structure using planarization to form a top surface

Method for forming a contact during the formation of a semiconductor device

Method for forming a capacitor wherein the first capacitor plate includes electrically coupled conductive layers separated by an intervening insulative layer

Method of forming recessed container cells

Isolated interconnect studs and method for forming the same

Etch aided by electrically shorting upper and lower sidewall portions during the formation of a semiconductor device

Recessed container cells and method of forming the same

Formation of a self-aligned structure

Process and apparatus for improving the performance of a temperature-sensitive etch process

Self-limiting method of reducing contamination in a contact opening, method of making contacts and semiconductor devices therewith, and resulting structures

Method of removing surface defects or other recesses during the formation of a semiconductor device

Method for forming a contact during the formation of a semiconductor device

Method of removing surface defects or other recesses during the formation of a semiconductor device

Capacitor and method for forming a capacitor

Plasma etching methods and contact opening forming methods

Etch aided by electrically shorting upper and lower sidewall portions during the formation of a semiconductor device

Process for using photo-definable layers in the manufacture of semiconductor devices and resulting structures of same

APPLIED MATERIALS INC

Methods for cyclically etching a metal layer for an interconnection structure for semiconductor applications

Chamber body design architecture for next generation advanced plasma technology

Chamber body design architecture for next generation advanced plasma technology

LAM RES CORP

Electrical and optical system and methods for monitoring erosion of electrostatic chuck edge bead materials

Optical system and methods for monitoring erosion of electrostatic chuck edge bead materials

LI LI

Method of controlling striations and CD loss in contact oxide etch