Etch aided by electrically shorting upper and lower sidewall portions during the formation of a semiconductor device

Abstract

A method used to fabricate a semiconductor device comprises etching a dielectric which results in an undesirable charge buildup along a sidewall formed in the dielectric during the etch. The charge buildup along a top and a bottom of the sidewall can reduce the etch rate thereby resulting in excessive etch times and undesirable etch opening profiles. To remove the charge, a sacrificial conductive layer is formed which electrically shorts the upper and lower portions of the sidewall and eliminates the charge. In another embodiment, a gas is used to remove the charge. After removing the charge, the dielectric etch may continue. Various embodiments of the inventive process and in-process structures are described.

What is claimed is:  
     
       1. A method used in the fabrication of a semiconductor device comprising: 
       providing a dielectric layer at a location over a conductive feature;  
       only partially etching said dielectric layer over said conductive feature to form a sidewall in said dielectric layer, said sidewall having upper and lower portions;  
       providing a conductive layer electrically which shorts said upper portion of said sidewall to said lower portion of said sidewall;  
       subsequent to providing said conductive layer, further etching said dielectric layer to expose said conductive feature; and  
       removing said conductive layer from said upper and lower sidewalls.  
     
     
       2. The method of  claim 1  further comprising removing said conductive layer from said upper and lower sidewalls subsequent to further etching said dielectric layer. 
     
     
       3. The method of  claim 2  further comprising oxidizing said conductive layer to remove said conductive layer from said upper and lower sidewalls. 
     
     
       4. The method of  claim 2  further comprising etching said conductive layer to remove said conductive layer from said upper and lower sidewalls. 
     
     
       5. A method used to form a semiconductor device comprising: 
       providing a first dielectric layer at a location over a conductive feature;  
       providing a second dielectric layer over said first dielectric layer and over said conductive feature;  
       etching said second dielectric layer to form an opening therein which exposes said first dielectric layer;  
       only partially etching said first dielectric layer to form an opening therein, wherein said openings in said first and second dielectric layers are defined by an upper sidewall portion in said second dielectric layer and a lower sidewall portion in said first dielectric layer;  
       forming a conductive spacer which contacts said upper sidewall portion in said second dielectric layer and said lower sidewall portion in said first dielectric layer to electrically short said upper sidewall portion to said lower sidewall portion;  
       subsequent to electrically shorting said upper sidewall portion and said lower sidewall portion, further etching said first dielectric layer to expose said conductive feature; and  
       removing said conductive spacer.  
     
     
       6. The method of  claim 5  further comprising oxidizing said conductive spacer to remove said conductive spacer.