Inventor

HELM MARK A

US77 patents

⚠️ This page may combine multiple inventors who share the name “HELM MARK A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HELM MARK A

MICRON TECHNOLOGY INC

Source lines for NAND memory devices

Methods of forming gated semiconductor assemblies

Efficient fabrication process for dual well type structures

Memory devices with local and global devices at substantially the same level above stacked tiers of memory cells and methods

Methods and apparatus having multiple select gates of different ranges of threshold voltages connected in series with memory cells

Threshold voltage distribution determination

Sense operation in a memory device

Boosted channel programming of memory

Data line arrangement and pillar arrangement in apparatuses

Source lines for NAND memory devices

Reduction of field edge thinning in peripheral devices

Reduction of field edge thinning in peripheral devices

Interconnecting conductive layers of memory devices

Gated semiconductor assemblies

Method of forming an array of FLASH field effect transistors and circuitry peripheral to such array

Efficient fabrication process for dual well type structures

Adjustment of code rate as function of memory endurance state metric

Multi-layer code rate architecture for copyback between partitions with different code rates

Acceleration of data queries in memory

Implementing variable number of bits per cell on storage devices

Separate partition for buffer and snapshot memory

Partitions within snapshot memory for buffer and snapshot memory

Threshold voltage distribution adjustment for buffer

Acceleration of data queries in memory

Apparatuses and methods for generating probabilistic information with current integration sensing

Data line arrangement and pillar arrangement in apparatuses

Adjustment of code rate as function of memory endurance state metric

Implementing variable number of bits per cell on storage devices

Apparatuses and methods for generating probabilistic information with current integration sensing

Memory devices with local and global devices at substantially the same level above stacked tiers of memory cells and methods

Methods, devices, and systems for data sensing

Interconnecting conductive layers of memory devices

Methods of forming an array of flash field effect transistors and circuitry peripheral to such array

Method of forming an array of FLASH field effect transistors and circuitry peripheral to such array

Implementing fault tolerant page stripes on low density memory systems

Separate partition for buffer and snapshot memory

Partitions within snapshot memory for buffer and snapshot memory

Read voltage calibration for copyback operation

Threshold voltage distribution adjustment for buffer

Trims corresponding to logical unit quantity

Partitioned memory having error detection capability

Implementing fault tolerant page stripes on low density memory systems

Read voltage calibration for copyback operation

GOLDMAN MATTHEW

Memory cell sensing

Memory devices and operating methods for a memory device

LODESTAR LICENSING GROUP LLC

Acceleration of data queries in memory

Partitioned memory having error detection capability

CYPRESS SEMICONDUCTOR CORP

Method for avoiding lithographic rounding effects for semiconductor fabrication

GODA AKIRA

Reducing effects of erase disturb in a memory device

HELM MARK A

Methods, devices, and systems for data sensing in a memory system