Inventor · disambiguated record
Abhijeet Chakraborty
Also filed as: CHAKRABORTY ABHIJEET
8 granted patents·444 citations·filing 1998–2022
89Inventor score
Technology areasG06F
Top patents by PatentIndex Score
8 records- 0191US6286128B1Method for design optimization using logical and physical informationMONTEREY DESIGN SYSTEMS INC·Filed 1998·Granted Sep 4, 2001·202 cites·10 claims
- 0288US6961916B2Placement method for integrated circuit design using topo-clusteringSYNOPSYS INC·Filed 2002·Granted Nov 1, 2005·45 cites·7 claims
- 0387US6442743B1Placement method for integrated circuit design using topo-clusteringMONTEREY DESIGN SYSTEMS·Filed 1998·Granted Aug 27, 2002·126 cites·13 claims
- 0479US10360341B2Integrated metal layer aware optimization of integrated circuit designsSYNOPSYS INC·Filed 2017·Granted Jul 23, 2019·4 cites·20 claims
- 0554US6367051B1System and method for concurrent buffer insertion and placement of logic gatesMONTEREY DESIGN SYSTEMS INC·Filed 1998·Granted Apr 2, 2002·31 cites·23 claims
- 0649US6192508B1Method for logic optimization for improving timing and congestion during placement in integrated circuit designMONTEREY DESIGN SYSTEMS·Filed 1998·Granted Feb 20, 2001·23 cites·18 claims
- 0748US12450415B2Library design and co-optimization with a circuit designSYNOPSYS INC·Filed 2022·Granted Oct 21, 2025·0 cites·20 claims
- 0839US6449756B1Method for accurate and efficient updates of timing information logic synthesis, placement and routing for integrated circuit designMONTEREY DESIGN SYSTEMS·Filed 1998·Granted Sep 10, 2002·13 cites·23 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →