Inventor · disambiguated record
Akshey Sehgal
Also filed as: SEHGAL AKSHEY
16 granted patents·8 pending applications·77 citations·filing 2003–2018
91Inventor score
Top patents by PatentIndex Score
24 records- 0196US10347528B1Interconnect formation process using wire trench etch prior to via etch, and related interconnectGLOBALFOUNDRIES INC·Filed 2018·Granted Jul 9, 2019·21 cites·12 claims
- 0294US9117822B1Methods and structures for back end of line integrationGLOBALFOUNDRIES INC·Filed 2014·Granted Aug 25, 2015·16 cites·10 claims
- 0392US9576894B2Integrated circuits including organic interlayer dielectric layers and methods for fabricating the sameGLOBALFOUNDRIES INC·Filed 2015·Granted Feb 21, 2017·9 cites·20 claims
- 0489US9105478B2Devices and methods of forming fins at tight fin pitchesGLOBALFOUNDRIES INC·Filed 2013·Granted Aug 11, 2015·9 cites·10 claims
- 0583US9121890B2Planar metrology pad adjacent a set of fins of a fin field effect transistor deviceGLOBALFOUNDRIES INC·Filed 2013·Granted Sep 1, 2015·5 cites·15 claims
- 0682US8969932B2Methods of forming a finfet semiconductor device with undoped finsGLOBALFOUNDRIES INC·Filed 2012·Granted Mar 3, 2015·6 cites·26 claims
- 0780US9105507B2Methods of forming a FinFET semiconductor device with undoped finsGLOBALFOUNDRIES INC·Filed 2015·Granted Aug 11, 2015·3 cites·20 claims
- 0877US9129905B2Planar metrology pad adjacent a set of fins of a fin field effect transistor deviceGLOBALFOUNDRIES INC·Filed 2013·Granted Sep 8, 2015·3 cites·15 claims
- 0975US10181420B2Devices with chamfer-less vias multi-patterning and methods for forming chamfer-less viasGLOBALFOUNDRIES INC·Filed 2017·Granted Jan 15, 2019·2 cites·10 claims
- 1070US10818557B2Integrated circuit structure to reduce soft-fail incidence and method of forming sameGLOBALFOUNDRIES INC·Filed 2018·Granted Oct 27, 2020·1 cites·19 claims
- 1168US10134876B2FinFETs with strained channels and reduced on state resistanceGLOBALFOUNDRIES INC·Filed 2017·Granted Nov 20, 2018·1 cites·15 claims
- 1253US8835233B2FinFET structure with multiple workfunctions and method for fabricating the sameWEI ANDY C·Filed 2012·Granted Sep 16, 2014·1 cites·20 claims
- 1352US9293363B2Methods and structures for back end of line integrationGLOBALFOUNDRIES INC·Filed 2015·Granted Mar 22, 2016·0 cites·7 claims
- 1451US10714380B2Method of forming smooth sidewall structures using spacer materialsGLOBALFOUNDRIES INC·Filed 2018·Granted Jul 14, 2020·0 cites·20 claims
- 1550US10121711B2Planar metrology pad adjacent a set of fins of a fin field effect transistor deviceGLOBALFOUNDRIES INC·Filed 2015·Granted Nov 6, 2018·0 cites·13 claims
- 1649US2017025347A1Methods and structures for back end of line integrationGLOBALFOUNDRIES INC·Filed 2016·Application pending·0 cites
- 1745US9281249B2Decoupling measurement of layer thicknesses of a plurality of layers of a circuit structureGLOBALFOUNDRIES INC·Filed 2014·Granted Mar 8, 2016·0 cites·22 claims
- 1845US2015348913A1Planar metrology pad adjacent a set of fins in a fin field effect transistor deviceGLOBALFOUNDRIES INC·Filed 2015·Application pending·0 cites
- 1945US2015287595A1Devices and methods of forming fins at tight fin pitchesGLOBALFOUNDRIES INC·Filed 2015·Application pending·0 cites
- 2045US2012067396A1Hydrophobic Solar Concentrator and Method of Using and Forming the Hydrophobic Solar ConcentratorYEGNASHANKARAN VISVAMOHAN·Filed 2010·Application pending·0 cites
- 2143US2015270175A1Partially crystallized fin hard mask for fin field-effect-transistor (finfet) deviceGLOBALFOUNDRIES INC·Filed 2014·Application pending·0 cites
- 2241US2015255353A1Forming source/drain regions with single reticle and resulting deviceGLOBALFOUNDRIES INC·Filed 2014·Application pending·0 cites
- 2337US2004050406A1Compositions and method for removing photoresist and/or resist residue at pressures ranging from ambient to supercriticalFiled 2003·Application pending·0 cites
- 2430US2012034756A1Method of Forming a Deep Trench Isolation Structure Using a Planarized Hard MaskKWON TAEHUN·Filed 2010·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →