Devices and methods of forming fins at tight fin pitches

Abstract

Devices and methods for forming semiconductor devices with fins at tight fin pitches are provided. One method includes, for instance: obtaining an intermediate semiconductor device; growing an epi layer over the substrate; forming a doped layer below the epi layer; depositing a first oxide layer on the epi layer; applying a dielectric material on the first oxide layer; and depositing a lithography stack on the dielectric material. One intermediate semiconductor device includes, for instance: a substrate with at least one n-well region and at least one p-well region; a doped layer over the substrate; an epi layer over the doped layer; a first oxide layer over the epi layer; a dielectric layer over the first oxide layer; and a lithography stack over the dielectric layer.

What is claimed is: 
     
         1 . An intermediate semiconductor device comprising:
 a substrate with at least one n-well region and at least one p-well region;   a doped layer over the substrate;   an epi layer over the doped layer;   a first oxide layer over the epi layer;   a dielectric layer over the first oxide layer; and   a lithography stack over the dielectric layer.   
     
     
         2 . The device of  claim 1 , wherein the lithography stack comprises:
 a sacrificial mandrel material on the dielectric material; and   a sacrificial layer on the sacrificial mandrel material.   
     
     
         3 . The device of  claim 2 , wherein the sacrificial mandrel material is an amorphous carbon. 
     
     
         4 . The device of  claim 2 , wherein the sacrificial layer is SiON. 
     
     
         5 . The device of  claim 1 , wherein the lithography stack comprises:
 a second oxide layer on the dielectric material;   a sacrificial mandrel material on the dielectric material; and   a sacrificial layer on the sacrificial mandrel material.   
     
     
         6 . The device of  claim 5 , wherein the sacrificial mandrel material is an amorphous carbon. 
     
     
         7 . The device of  claim 5 , wherein the sacrificial layer is SiON. 
     
     
         8 . The device of  claim 1 , wherein the lithography stack comprises:
 a second oxide layer on the dielectric material.   
     
     
         9 . The device of  claim 1 , wherein the first oxide layer is a nitride layer. 
     
     
         10 . The device of  claim 1 , wherein the dielectric layer is a high-k material. 
     
     
         11 . The device of  claim 1 , wherein the dielectric layer is selected from HfO 2 , Al 2 O 3 , HfAlO 2 , and ZrO. 
     
     
         12 . The device of  claim 1 , wherein the lithography stack comprises:
 an organic planarization layer over the dielectric layer;   a silicon containing anti-reflective coating layer over the organic planarization layer; and   a photoresist layer over the silicon containing anti-reflective coating layer.