Inventor · disambiguated record
Alok Tripathi
Also filed as: TRIPATHI ALOK · TRIPATHI ALOK KUMAR
16 granted patents·2 pending applications·198 citations·filing 1992–2019
92Inventor score
Files withINTEL CORP7ST MICROELECTRONICS INT NV4CADENCE DESIGN SYSTEMS INC2ST MICROELECTRONICS SA2TRIPATHI ALOK1
Top patents by PatentIndex Score
18 records- 0196US7402048B2Technique for blind-mating daughtercard to mainboardINTEL CORP·Filed 2006·Granted Jul 22, 2008·68 cites·12 claims
- 0291US7490309B1Method and system for automatically optimizing physical implementation of an electronic circuit responsive to simulation analysisCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Feb 10, 2009·31 cites·24 claims
- 0387US10585143B2Flip flop of a digital electronic chipST MICROELECTRONICS SA·Filed 2018·Granted Mar 10, 2020·4 cites·20 claims
- 0479US5254210AMethod and apparatus for growing semiconductor heterostructuresUS ARMY·Filed 1992·Granted Oct 19, 1993·33 cites·20 claims
- 0577US9785141B2Method, system, and computer program product for schematic driven, unified thermal and electromagnetic interference compliance analyses for electronic circuit designsCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Oct 10, 2017·6 cites·20 claims
- 0671US10153754B2Method for managing the operation of a low-complexity synchronous retention flip-flop circuit, and corresponding circuitST MICROELECTRONICS INT NV·Filed 2017·Granted Dec 11, 2018·2 cites·22 claims
- 0770US6710266B2Add-in card edge-finger design/stackup to optimize connector performanceINTEL CORP·Filed 2002·Granted Mar 23, 2004·17 cites·20 claims
- 0868US7307492B2Design, layout and method of manufacture for a circuit that taps a differential signalINTEL CORP·Filed 2002·Granted Dec 11, 2007·13 cites·16 claims
- 0961US6700455B2Electromagnetic emission reduction technique for shielded connectorsINTEL CORP·Filed 2001·Granted Mar 2, 2004·12 cites·17 claims
- 1059US7391829B2Apparatus, system and method for receiver equalizationINTEL CORP·Filed 2003·Granted Jun 24, 2008·7 cites·20 claims
- 1157US6801043B2Time domain reflectometry based transmitter equalizationINTEL CORP·Filed 2002·Granted Oct 5, 2004·4 cites·25 claims
- 1249US8601422B2Method and system for schematic-visualization driven topologically-equivalent layout design in RFSiPTRIPATHI ALOK·Filed 2008·Granted Dec 3, 2013·1 cites·22 claims
- 1345US10637447B2Low voltage, master-slave flip-flopST MICROELECTRONICS INT NV·Filed 2019·Granted Apr 28, 2020·0 cites·19 claims
- 1445US9401715B1Conditional pulse generator circuit for low power pulse triggered flip flopST MICROELECTRONICS INT NV·Filed 2015·Granted Jul 26, 2016·0 cites·22 claims
- 1544US2005201454A1System and method for automatically calibrating two-tap and multi-tap equalization for a communications linkINTEL CORP·Filed 2004·Application pending·0 cites
- 1642US10277207B1Low voltage, master-slave flip-flopST MICROELECTRONICS INT NV·Filed 2018·Granted Apr 30, 2019·0 cites·16 claims
- 1736US2006291552A1Decision feedback equalizerYEUNG EVELINA F·Filed 2005·Application pending·0 cites
- 1835US10263603B2Method for managing the operation of a synchronous retention flip-flop circuit exhibiting an ultra-low leakage current, and corresponding circuitST MICROELECTRONICS SA·Filed 2017·Granted Apr 16, 2019·0 cites·14 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →