Inventor · disambiguated record
Andre P. Labonte
Also filed as: LABONTE ANDRE · LABONTE ANDRE P · LABONTE ANDRE PAUL
56 granted patents·6 pending applications·405 citations·filing 2003–2024
98Inventor score
Top patents by PatentIndex Score
62 records- 0199US10026824B1Air-gap gate sidewall spacer and methodGLOBALFOUNDRIES INC·Filed 2017·Granted Jul 17, 2018·53 cites·17 claims
- 0298US10243053B1Gate contact structure positioned above an active region of a transistor deviceGLOBALFOUNDRIES INC·Filed 2018·Granted Mar 26, 2019·33 cites·20 claims
- 0398US9824921B1Method and apparatus for placing a gate contact inside a semiconductor active region having high-k dielectric gate capsGLOBALFOUNDRIES INC·Filed 2016·Granted Nov 21, 2017·32 cites·10 claims
- 0498US9397049B1Gate tie-down enablement with inner spacerIBM·Filed 2015·Granted Jul 19, 2016·25 cites·14 claims
- 0597US11112694B2Methods of forming variable-depth device structuresAPPLIED MATERIALS INC·Filed 2020·Granted Sep 7, 2021·5 cites·27 claims
- 0697US9929048B1Middle of the line (MOL) contacts with two-dimensional self-alignmentGLOBALFOUNDRIES INC·Filed 2016·Granted Mar 27, 2018·22 cites·20 claims
- 0797US9780178B2Methods of forming a gate contact above an active region of a semiconductor deviceGLOBALFOUNDRIES INC·Filed 2015·Granted Oct 3, 2017·17 cites·12 claims
- 0897US9691897B2Three-dimensional semiconductor transistor with gate contact in active regionGLOBALFOUNDRIES INC·Filed 2015·Granted Jun 27, 2017·22 cites·5 claims
- 0997US9490317B1Gate contact structure having gate contact layerGLOBALFOUNDRIES INC·Filed 2015·Granted Nov 8, 2016·29 cites·16 claims
- 1097US9324656B1Methods of forming contacts on semiconductor devices and the resulting devicesGLOBALFOUNDRIES INC·Filed 2015·Granted Apr 26, 2016·18 cites·16 claims
- 1196US9941278B2Method and apparatus for placing a gate contact inside an active region of a semiconductorGLOBALFOUNDRIES INC·Filed 2016·Granted Apr 10, 2018·13 cites·20 claims
- 1295US9502286B2Methods of forming self-aligned contact structures on semiconductor devices and the resulting devicesGLOBALFOUNDRIES INC·Filed 2015·Granted Nov 22, 2016·14 cites·20 claims
- 1393US10566201B1Gate cut method after source/drain metallizationGLOBALFOUNDRIES INC·Filed 2018·Granted Feb 18, 2020·6 cites·17 claims
- 1492US9947589B1Methods of forming a gate contact for a transistor above an active region and the resulting deviceGLOBALFOUNDRIES INC·Filed 2017·Granted Apr 17, 2018·8 cites·19 claims
- 1592US9735054B2Gate tie-down enablement with inner spacerIBM·Filed 2016·Granted Aug 15, 2017·4 cites·20 claims
- 1691US9570397B1Local interconnect structure including non-eroded contact via trenchesIBM·Filed 2015·Granted Feb 14, 2017·7 cites·14 claims
- 1791US9478662B2Gate and source/drain contact structures for a semiconductor deviceGLOBALFOUNDRIES INC·Filed 2016·Granted Oct 25, 2016·6 cites·19 claims
- 1889US9455254B2Methods of forming a combined gate and source/drain contact structure and the resulting deviceGLOBALFOUNDRIES INC·Filed 2014·Granted Sep 27, 2016·10 cites·23 claims
- 1986US9640625B2Self-aligned gate contact formationGLOBALFOUNDRIES INC·Filed 2014·Granted May 2, 2017·8 cites·14 claims
- 2085US8507375B1Alignment tolerant semiconductor contact and methodLABONTE ANDRE P·Filed 2012·Granted Aug 13, 2013·8 cites·16 claims
- 2184US10879375B2Gate tie-down enablement with inner spacerIBM·Filed 2019·Granted Dec 29, 2020·1 cites·20 claims
- 2284US10249728B2Air-gap gate sidewall spacer and methodGLOBALFOUNDRIES INC·Filed 2018·Granted Apr 2, 2019·3 cites·18 claims
- 2384US8004032B1System and method for providing low voltage high density multi-bit storage flash memoryNAT SEMICONDUCTOR CORP·Filed 2006·Granted Aug 23, 2011·10 cites·22 claims
- 2483US10204994B2Methods of forming a semiconductor device with a gate contact positioned above the active regionGLOBALFOUNDRIES INC·Filed 2017·Granted Feb 12, 2019·4 cites·18 claims
- 2583US10014215B2Method and apparatus for placing a gate contact inside a semiconductor active region having high-k dielectric gate capsGLOBALFOUNDRIES INC·Filed 2017·Granted Jul 3, 2018·3 cites·10 claims
- 2682US12158605B2Method for manufacturing optical device structuresAPPLIED MATERIALS INC·Filed 2024·Granted Dec 3, 2024·0 cites·20 claims
- 2778US9627257B2Gate tie-down enablement with inner spacerIBM·Filed 2016·Granted Apr 18, 2017·1 cites·20 claims
- 2877US7968418B1Apparatus and method for isolating integrated circuit components using deep trench isolation and shallow trench isolationNAT SEMICONDUCTOR CORP·Filed 2007·Granted Jun 28, 2011·8 cites·20 claims
- 2976US12013566B2Method for manufacturing optical device structuresAPPLIED MATERIALS INC·Filed 2022·Granted Jun 18, 2024·0 cites·20 claims
- 3076US10879073B2Insulating gate separation structure for transistor devicesGLOBALFOUNDRIES INC·Filed 2019·Granted Dec 29, 2020·1 cites·20 claims
- 3176US10790376B2Contact structuresGLOBALFOUNDRIES INC·Filed 2018·Granted Sep 29, 2020·2 cites·17 claims
- 3274US10211100B2Methods of forming an air gap adjacent a gate of a transistor and a gate contact above the active region of the transistorGLOBALFOUNDRIES INC·Filed 2017·Granted Feb 19, 2019·2 cites·20 claims
- 3373US8580628B2Integrated circuit contact structure and methodLABONTE ANDRE P·Filed 2012·Granted Nov 12, 2013·4 cites·11 claims
- 3471US10770585B2Self-aligned buried contact for vertical field-effect transistor and method of production thereofGLOBALFOUNDRIES INC·Filed 2018·Granted Sep 8, 2020·1 cites·10 claims
- 3570US10468300B2Contacting source and drain of a transistor deviceGLOBALFOUNDRIES INC·Filed 2017·Granted Nov 5, 2019·1 cites·8 claims
- 3670US8377788B2SiGe heterojunction bipolar transistor and method of forming a SiGe heterojunction bipolar transistorNAT SEMICONDUCTOR CORP·Filed 2010·Granted Feb 19, 2013·4 cites·14 claims
- 3769US10832961B1Sacrificial gate spacer regions for gate contacts formed over the active region of a transistorIBM·Filed 2019·Granted Nov 10, 2020·1 cites·17 claims
- 3869US10522654B2Gate tie-down enablement with inner spacerIBM·Filed 2018·Granted Dec 31, 2019·0 cites·19 claims
- 3968US7781295B1System and method for providing a single deposition emitter/base in a bipolar junction transistorNAT SEMICONDUCTOR CORP·Filed 2006·Granted Aug 24, 2010·4 cites·20 claims
- 4067US11487058B2Method for manufacturing optical device structuresAPPLIED MATERIALS INC·Filed 2020·Granted Nov 1, 2022·0 cites·20 claims
- 4167US10332977B2Gate tie-down enablement with inner spacerIBM·Filed 2018·Granted Jun 25, 2019·0 cites·20 claims
- 4266US9929049B2Gate tie-down enablement with inner spacerIBM·Filed 2017·Granted Mar 27, 2018·0 cites·20 claims
- 4365US10128352B2Gate tie-down enablement with inner spacerIBM·Filed 2017·Granted Nov 13, 2018·0 cites·19 claims
- 4465US9941163B2Gate tie-down enablement with inner spacerIBM·Filed 2017·Granted Apr 10, 2018·0 cites·18 claims
- 4565US9899259B2Gate tie-down enablement with inner spacerIBM·Filed 2017·Granted Feb 20, 2018·0 cites·18 claims
- 4665US9460963B2Self-aligned contacts and methods of fabricationGLOBALFOUNDRIES INC·Filed 2014·Granted Oct 4, 2016·1 cites·17 claims
- 4764US8007675B1System and method for controlling an etch process for a single crystal having a buried layerNAT SEMICONDUCTOR CORP·Filed 2005·Granted Aug 30, 2011·2 cites·20 claims
- 4863US7829429B1Semiconductor device having localized insulated block in bulk substrate and related methodNAT SEMICONDUCTOR CORP·Filed 2007·Granted Nov 9, 2010·2 cites·20 claims
- 4962US7175777B1Method of forming a sub-micron tip featureNAT SEMICONDUCTOR CORP·Filed 2003·Granted Feb 13, 2007·7 cites·12 claims
- 5061US7858428B1Method for forming a lens using sub-micron horizontal tip featureNAT SEMICONDUCTOR CORP·Filed 2005·Granted Dec 28, 2010·2 cites·23 claims
Showing the top 50 of 62 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →