Inventor · disambiguated record
Balasubramanian Pranatharthiharan
Also filed as: PRANATHARTHIHARAN BALASUBRAMAN · PRANATHARTHIHARAN BALASUBRAMANIAN · PRANATHARTHIHARAN BALASUBRAMANIAN S
216 granted patents·77 pending applications·960 citations·filing 2005–2025
99Inventor score
Files withIBM192APPLIED MATERIALS INC62GLOBALFOUNDRIES INC16ADEIA SEMICONDUCTOR SOLUTIONS LLC5ST MICROELECTRONICS INC5
Top patents by PatentIndex Score
293 records- 0198US11538720B2Stacked transistors with different channel widthsTESSERA LLC·Filed 2020·Granted Dec 27, 2022·5 cites·17 claims
- 0298US10505111B1Confined phase change memory with double air gapIBM·Filed 2018·Granted Dec 10, 2019·37 cites·20 claims
- 0398US9721848B1Cutting fins and gates in CMOS devicesIBM·Filed 2016·Granted Aug 1, 2017·32 cites·20 claims
- 0498US9660028B1Stacked transistors with different channel widthsIBM·Filed 2016·Granted May 23, 2017·93 cites·16 claims
- 0598US9570555B1Source and drain epitaxial semiconductor material integration for high voltage semiconductor devicesIBM·Filed 2015·Granted Feb 14, 2017·22 cites·15 claims
- 0698US9443853B1Minimizing shorting between FinFET epitaxial regionsIBM·Filed 2015·Granted Sep 13, 2016·17 cites·16 claims
- 0798US9431399B1Method for forming merged contact for semiconductor deviceIBM·Filed 2015·Granted Aug 30, 2016·31 cites·20 claims
- 0898US9337094B1Method of forming contact useful in replacement metal gate processing and related semiconductor structureIBM·Filed 2015·Granted May 10, 2016·38 cites·19 claims
- 0998US9064801B1Bi-layer gate cap for self-aligned contact formationIBM·Filed 2014·Granted Jun 23, 2015·49 cites·17 claims
- 1097US12057371B2Semiconductor device with early buried power rail (BPR) and backside power distribution network (BSPDN)IBM·Filed 2021·Granted Aug 6, 2024·5 cites·12 claims
- 1197US9741823B1Fin cut during replacement gate formationIBM·Filed 2016·Granted Aug 22, 2017·22 cites·10 claims
- 1297US9704753B2Minimizing shorting between FinFET epitaxial regionsIBM·Filed 2016·Granted Jul 11, 2017·10 cites·17 claims
- 1397US9397006B1Co-integration of different fin pitches for logic and analog devicesIBM·Filed 2015·Granted Jul 19, 2016·25 cites·20 claims
- 1496US11894436B2Gate-all-around monolithic stacked field effect transistors having multiple threshold voltagesIBM·Filed 2021·Granted Feb 6, 2024·3 cites·14 claims
- 1596US9923078B2Trench silicide contacts with high selectivity processIBM·Filed 2015·Granted Mar 20, 2018·14 cites·8 claims
- 1696US9685340B2Stable contact on one-sided gate tie-down structureIBM·Filed 2015·Granted Jun 20, 2017·17 cites·17 claims
- 1796US9590074B1Method to prevent lateral epitaxial growth in semiconductor devicesIBM·Filed 2015·Granted Mar 7, 2017·11 cites·7 claims
- 1896US9583489B1Solid state diffusion doping for bulk finFET devicesIBM·Filed 2016·Granted Feb 28, 2017·17 cites·17 claims
- 1996US9472447B1Confined eptaxial growth for continued pitch scalingIBM·Filed 2015·Granted Oct 18, 2016·14 cites·14 claims
- 2096US9431486B1Channel strain and controlling lateral epitaxial growth of the source and drain in FinFET devicesIBM·Filed 2015·Granted Aug 30, 2016·13 cites·20 claims
- 2195US10998234B2Nanosheet bottom isolation and source or drain epitaxial growthIBM·Filed 2019·Granted May 4, 2021·11 cites·20 claims
- 2295US9935168B2Gate contact with vertical isolation from source-drainIBM·Filed 2017·Granted Apr 3, 2018·8 cites·20 claims
- 2395US9691765B1Fin type field effect transistors with different pitches and substantially uniform fin revealIBM·Filed 2016·Granted Jun 27, 2017·12 cites·14 claims
- 2495US9595592B1Forming dual contact silicide using metal multi-layer and ion beam mixingIBM·Filed 2015·Granted Mar 14, 2017·11 cites·16 claims
- 2595US9305923B1Low resistance replacement metal gate structureIBM·Filed 2014·Granted Apr 5, 2016·18 cites·11 claims
- 2694US10134760B2FinFETs with various fin heightIBM·Filed 2017·Granted Nov 20, 2018·8 cites·10 claims
- 2794US9997418B2Dual liner silicideIBM·Filed 2016·Granted Jun 12, 2018·8 cites·18 claims
- 2894US9853056B1Strained CMOS on strain relaxation buffer substrateIBM·Filed 2016·Granted Dec 26, 2017·7 cites·8 claims
- 2994US9806078B1FinFET spacer formation on gate sidewalls, between the channel and source/drain regionsGLOBALFOUNDRIES INC·Filed 2016·Granted Oct 31, 2017·9 cites·17 claims
- 3094US9576961B2Semiconductor devices with sidewall spacers of equal thicknessIBM·Filed 2015·Granted Feb 21, 2017·6 cites·9 claims
- 3194US9576954B1POC process flow for conformal recess fillIBM·Filed 2015·Granted Feb 21, 2017·8 cites·10 claims
- 3294US9530890B1Parasitic capacitance reductionIBM·Filed 2015·Granted Dec 27, 2016·9 cites·6 claims
- 3394US9461168B1Channel strain and controlling lateral epitaxial growth of the source and drain in FinFET devicesIBM·Filed 2016·Granted Oct 4, 2016·8 cites·1 claims
- 3494US9147576B2Gate contact with vertical isolation from source-drainIBM·Filed 2014·Granted Sep 29, 2015·12 cites·17 claims
- 3594US9034741B2Halo region formation by epitaxial growthIBM·Filed 2013·Granted May 19, 2015·15 cites·20 claims
- 3694US8753970B2Methods of forming semiconductor devices with self-aligned contacts and the resulting devicesXIE RUILONG·Filed 2012·Granted Jun 17, 2014·24 cites·13 claims
- 3793US12268031B2Backside power rails and power distribution network for density scalingIBM·Filed 2021·Granted Apr 1, 2025·2 cites·12 claims
- 3893US9882050B1Strained CMOS on strain relaxation buffer substrateIBM·Filed 2017·Granted Jan 30, 2018·6 cites·3 claims
- 3993US9293551B2Integrated multiple gate length semiconductor device including self-aligned contactsIBM·Filed 2013·Granted Mar 22, 2016·12 cites·14 claims
- 4092US11942426B2Semiconductor structure having alternating selective metal and dielectric layersIBM·Filed 2021·Granted Mar 26, 2024·2 cites·19 claims
- 4192US10832964B1Replacement contact formation for gate contact over active region with selective metal growthIBM·Filed 2019·Granted Nov 10, 2020·8 cites·20 claims
- 4292US10615257B2Patterning method for nanosheet transistorsIBM·Filed 2018·Granted Apr 7, 2020·7 cites·20 claims
- 4392US10256296B2Middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stackIBM·Filed 2015·Granted Apr 9, 2019·5 cites·11 claims
- 4492US9985024B2Minimizing shorting between FinFET epitaxial regionsIBM·Filed 2017·Granted May 29, 2018·4 cites·17 claims
- 4592US9887289B2Method and structure of improving contact resistance for passive and long channel devicesIBM·Filed 2015·Granted Feb 6, 2018·6 cites·9 claims
- 4692US9852951B2Minimizing shorting between FinFET epitaxial regionsIBM·Filed 2016·Granted Dec 26, 2017·4 cites·20 claims
- 4792US9698101B2Self-aligned local interconnect technologyIBM·Filed 2015·Granted Jul 4, 2017·6 cites·19 claims
- 4892US9406767B1POC process flow for conformal recess fillIBM·Filed 2016·Granted Aug 2, 2016·6 cites·1 claims
- 4991US10242981B2Fin cut during replacement gate formationIBM·Filed 2017·Granted Mar 26, 2019·5 cites·17 claims
- 5091US9871099B2Nanosheet isolation for bulk CMOS non-planar devicesIBM·Filed 2015·Granted Jan 16, 2018·6 cites·19 claims
Showing the top 50 of 293 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →