Inventor · disambiguated record
Brent Bean
Also filed as: BEAN BRENT · BEAN BRENT L
40 granted patents·2 pending applications·125 citations·filing 1992–2020
97Inventor score
Top patents by PatentIndex Score
42 records- 0191US9967092B2Key expansion logic using decryption key primitivesVIA TECH INC·Filed 2015·Granted May 8, 2018·10 cites·21 claims
- 0288US9911008B2Microprocessor with on-the-fly switching of decryption keysVIA TECH INC·Filed 2015·Granted Mar 6, 2018·6 cites·15 claims
- 0388US9507404B2Single core wakeup multi-core synchronization mechanismVIA TECH INC·Filed 2014·Granted Nov 29, 2016·5 cites·18 claims
- 0486US9798898B2Microprocessor with secure execution mode and store key instructionsVIA TECH INC·Filed 2015·Granted Oct 24, 2017·5 cites·19 claims
- 0585US7975132B2Apparatus and method for fast correct resolution of call and return instructions using multiple call/return stacks in the presence of speculative conditional instruction execution in a pipelined microprocessorVIA TECH INC·Filed 2009·Granted Jul 5, 2011·12 cites·25 claims
- 0684US9892283B2Decryption of encrypted instructions using keys selected on basis of instruction fetch addressVIA TECH INC·Filed 2015·Granted Feb 13, 2018·4 cites·20 claims
- 0784US8719589B2Microprocessor that facilitates task switching between multiple encrypted programs having different associated decryption key valuesHENRY G GLENN·Filed 2011·Granted May 6, 2014·4 cites·29 claims
- 0882US8074060B2Out-of-order execution microprocessor that selectively initiates instruction retirement earlyCOL GERARD M·Filed 2008·Granted Dec 6, 2011·13 cites·21 claims
- 0978US8886960B2Microprocessor that facilitates task switching between encrypted and unencrypted programsVIA TECH INC·Filed 2013·Granted Nov 11, 2014·2 cites·18 claims
- 1077US7203824B2Apparatus and method for handling BTAC branches that wrap across instruction cache linesIP FIRST LLC·Filed 2001·Granted Apr 10, 2007·24 cites·27 claims
- 1176US8639945B2Branch and switch key instruction in a microprocessor that fetches and decrypts encrypted instructionsHENRY G GLENN·Filed 2011·Granted Jan 28, 2014·2 cites·27 claims
- 1274US9372696B2Microprocessor with compressed and uncompressed microcode memoriesVIA TECH INC·Filed 2013·Granted Jun 21, 2016·3 cites·19 claims
- 1374US8521996B2Pipelined microprocessor with fast non-selective correct conditional branch instruction resolutionHENRY G GLENN·Filed 2009·Granted Aug 27, 2013·5 cites·24 claims
- 1473US7234045B2Apparatus and method for handling BTAC branches that wrap across instruction cache linesIP FIRST LLC·Filed 2005·Granted Jun 19, 2007·6 cites·20 claims
- 1572US9461818B2Method for encrypting a program for subsequent execution by a microprocessor configured to decrypt and execute the encrypted programVIA TECH INC·Filed 2013·Granted Oct 4, 2016·1 cites·18 claims
- 1671US8645714B2Branch target address cache for predicting instruction decryption keys in a microprocessor that fetches and decrypts encrypted instructionsHENRY G GLENN·Filed 2011·Granted Feb 4, 2014·1 cites·20 claims
- 1768US8423751B2Microprocessor with fast execution of call and return instructionsHENRY G GLENN·Filed 2009·Granted Apr 16, 2013·3 cites·21 claims
- 1865US10108431B2Method and apparatus for waking a single core of a multi-core microprocessor, while maintaining most cores in a sleep stateVIA TECH INC·Filed 2016·Granted Oct 23, 2018·0 cites·20 claims
- 1963US8635437B2Pipelined microprocessor with fast conditional branch instructions based on static exception stateHENRY G GLENN·Filed 2009·Granted Jan 21, 2014·1 cites·28 claims
- 2063US8281110B2Out-of-order microprocessor with separate branch information circular queue table tagged by branch instructions in reorder buffer to reduce unnecessary space in bufferMCDONALD THOMAS C·Filed 2009·Granted Oct 2, 2012·2 cites·26 claims
- 2161US8880902B2Microprocessor that securely decrypts and executes encrypted instructionsVIA TECH INC·Filed 2013·Granted Nov 4, 2014·0 cites·24 claims
- 2261US8850229B2Apparatus for generating a decryption key for use to decrypt a block of encrypted instruction data being fetched from an instruction cache in a microprocessorVIA TECH INC·Filed 2013·Granted Sep 30, 2014·0 cites·18 claims
- 2358US11567776B2Branch density detection for prefetcherCENTAUR TECH INC·Filed 2020·Granted Jan 31, 2023·0 cites·20 claims
- 2458US9798669B1System and method of determining memory ownership on cache line basis for detecting self-modifying codeVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2016·Granted Oct 24, 2017·0 cites·21 claims
- 2558US9798670B1System and method of determining memory ownership on cache line basis for detecting self-modifying code including modification of a cache line with an executing instructionVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2016·Granted Oct 24, 2017·0 cites·20 claims
- 2658US9798675B1System and method of determining memory ownership on cache line basis for detecting self-modifying code including code with looping instructionsVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2016·Granted Oct 24, 2017·0 cites·22 claims
- 2758US9792216B1System and method of determining memory ownership on cache line basis for detecting self-modifying code including code with instruction that overlaps cache line boundariesVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2016·Granted Oct 17, 2017·0 cites·21 claims
- 2856US8700919B2Switch key instruction in a microprocessor that fetches and decrypts encrypted instructionsHENRY G GLENN·Filed 2011·Granted Apr 15, 2014·0 cites·20 claims
- 2956US8683225B2Microprocessor that facilitates task switching between encrypted and unencrypted programsHENRY G GLENN·Filed 2011·Granted Mar 25, 2014·0 cites·10 claims
- 3056US8671285B2Microprocessor that fetches and decrypts encrypted instructions in same time as plain text instructionsHENRY G GLENN·Filed 2011·Granted Mar 11, 2014·0 cites·22 claims
- 3156US8245017B2Pipelined microprocessor with normal and fast conditional branch instructionsHENRY G GLENN·Filed 2009·Granted Aug 14, 2012·0 cites·34 claims
- 3256US8145890B2Pipelined microprocessor with fast conditional branch instructions based on static microcode-implemented instruction stateHENRY G GLENN·Filed 2009·Granted Mar 27, 2012·0 cites·29 claims
- 3356US8131984B2Pipelined microprocessor with fast conditional branch instructions based on static serializing instruction stateHENRY G GLENN·Filed 2009·Granted Mar 6, 2012·0 cites·33 claims
- 3455US9361097B2Selectively compressed microcodeVIA TECH INC·Filed 2013·Granted Jun 7, 2016·0 cites·21 claims
- 3555US7979675B2Pipelined microprocessor with fast non-selective correct conditional branch instruction resolutionVIA TECH INC·Filed 2009·Granted Jul 12, 2011·0 cites·27 claims
- 3652US9830155B2Microprocessor using compressed and uncompressed microcode storageVIA TECH INC·Filed 2016·Granted Nov 28, 2017·0 cites·15 claims
- 3750US10078581B2Processor with instruction cache that performs zero clock retiresVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2016·Granted Sep 18, 2018·0 cites·20 claims
- 3850US9483263B2Uncore microcode ROMVIA TECH INC·Filed 2013·Granted Nov 1, 2016·0 cites·20 claims
- 3948US10067875B2Processor with instruction cache that performs zero clock retiresVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2016·Granted Sep 4, 2018·0 cites·20 claims
- 4048US5319213AThermal target test boardUS ARMY·Filed 1992·Granted Jun 7, 1994·16 cites·13 claims
- 4147US2010205399A1Performance counter for microcode instruction executionVIA TECH INC·Filed 2009·Application pending·0 cites
- 4239US2012223038A1U-shaped shelfBEAN BRENT·Filed 2011·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Brent Bean files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →