Inventor · disambiguated record
Bradley Gene Burgess
Also filed as: BURGESS BRADLEY · BURGESS BRADLEY G · BURGESS BRADLEY GENE
26 granted patents·8 pending applications·873 citations·filing 1987–2025
97Inventor score
Top patents by PatentIndex Score
34 records- 0197US5034922AIntelligent electrically erasable, programmable read-only memory with improved read latencyMOTOROLA INC·Filed 1987·Granted Jul 23, 1991·129 cites·6 claims
- 0289US7024555B2Apparatus and method for unilaterally loading a secure operating system within a multiprocessor environmentINTEL CORP·Filed 2001·Granted Apr 4, 2006·50 cites·38 claims
- 0388US6202130B1Data processing system for processing vector data and method thereforMOTOROLA INC·Filed 1998·Granted Mar 13, 2001·162 cites·29 claims
- 0480US5448744AIntegrated circuit microprocessor with programmable chip select logicMOTOROLA INC·Filed 1989·Granted Sep 5, 1995·69 cites·36 claims
- 0579US6157998AMethod for performing branch prediction and resolution of two or more branch instructions within two or more branch prediction buffersMOTOROLA INC·Filed 1998·Granted Dec 5, 2000·83 cites·7 claims
- 0675US5392228AResult normalizer and method of operationMOTOROLA INC·Filed 1993·Granted Feb 21, 1995·67 cites·5 claims
- 0773US12293192B2Bundling and dynamic allocation of register blocks for vector instructionsSIFIVE INC·Filed 2023·Granted May 6, 2025·0 cites·21 claims
- 0872US5500943AData processor with rename buffer and FIFO buffer for in-order instruction completionMOTOROLA INC·Filed 1995·Granted Mar 19, 1996·66 cites·10 claims
- 0971US9836304B2Cumulative confidence fetch throttlingDENMAN MARVIN·Filed 2010·Granted Dec 5, 2017·5 cites·17 claims
- 1071US6477640B1Apparatus and method for predicting multiple branches and performing out-of-order branch resolutionMOTOROLA INC·Filed 2000·Granted Nov 5, 2002·15 cites·8 claims
- 1171US5361392ADigital computing system with low power mode and special bus cycle thereforMOTOROLA INC·Filed 1993·Granted Nov 1, 1994·60 cites·4 claims
- 1270US2025278271A1Transfer buffer between a scalar pipeline and vector pipelineSIFIVE INC·Filed 2025·Application pending·0 cites
- 1369US12373210B2Transfer buffer between a scalar pipeline and vector pipelineSIFIVE INC·Filed 2023·Granted Jul 29, 2025·0 cites·20 claims
- 1469US2025181355A1Dependency tracking and chaining for vector instructionsSIFIVE INC·Filed 2025·Application pending·0 cites
- 1569US2025251939A1Bundling and dynamic allocation of register blocks for vector instructionsSIFIVE INC·Filed 2025·Application pending·0 cites
- 1668US12204458B1Translation lookaside buffer probing preventionSIFIVE INC·Filed 2023·Granted Jan 21, 2025·0 cites·20 claims
- 1767US12493465B2Vector load store operations in a vector pipeline using a single operation in a load store unitSIFIVE INC·Filed 2023·Granted Dec 9, 2025·0 cites·20 claims
- 1867US9395988B2Micro-ops including packed source and destination fieldsSAMSUNG ELECTRONICS CO LTD·Filed 2013·Granted Jul 19, 2016·2 cites·32 claims
- 1967US6519683B2System and method for instruction cache re-orderingINTEL CORP·Filed 2000·Granted Feb 11, 2003·12 cites·25 claims
- 2065US6157999AData processing system having a synchronizing link stack and method thereofMOTOROLA INC·Filed 1997·Granted Dec 5, 2000·53 cites·15 claims
- 2163US7921293B2Apparatus and method for unilaterally loading a secure operating system within a multiprocessor environmentINTEL CORP·Filed 2006·Granted Apr 5, 2011·2 cites·18 claims
- 2263US5072365ADirect memory access controller using prioritized interrupts for varying bus mastershipMOTOROLA INC·Filed 1989·Granted Dec 10, 1991·30 cites·8 claims
- 2362US9424041B2Efficient way to cancel speculative ‘source ready’ in scheduler for direct and nested dependent instructionsSAMSUNG ELECTRONICS CO LTD·Filed 2013·Granted Aug 23, 2016·2 cites·19 claims
- 2459US9588770B2Dynamic rename based register reconfiguration of a vector register fileBURGESS BRADLEY GENE·Filed 2013·Granted Mar 7, 2017·2 cites·22 claims
- 2557US5408428AProgrammable bit cellMOTOROLA INC·Filed 1994·Granted Apr 18, 1995·33 cites·8 claims
- 2653US6950904B2Cache way replacement techniqueINTEL CORP·Filed 2002·Granted Sep 27, 2005·4 cites·40 claims
- 2753US2024160446A1Predicting a Vector Length Associated with a Configuration InstructionSIFIVE INC·Filed 2023·Application pending·0 cites
- 2851US8736308B2Pipeline power gatingBAILEY DANIEL W·Filed 2011·Granted May 27, 2014·1 cites·17 claims
- 2945US5642493AMethod of loading instructions into an instruction cache by repetitively using a routine containing a mispredicted branch instructionMOTOROLA INC·Filed 1994·Granted Jun 24, 1997·15 cites·12 claims
- 3045US2003229794A1System and method for protection against untrusted system management code by redirecting a system management interrupt and creating a virtual machine containerFiled 2002·Application pending·0 cites
- 3142US2020210626A1Secure branch predictor with context-specific learned instruction target address encryptionSAMSUNG ELECTRONICS CO LTD·Filed 2019·Application pending·0 cites
- 3241US2002087831A1Instruction packetization based on rename capacityFiled 2000·Application pending·0 cites
- 3339US2012059971A1Method and apparatus for handling critical blocking of store-to-load forwardingKAPLAN DAVID·Filed 2010·Application pending·0 cites
- 3437US5329621AMicroprocessor which optimizes bus utilization based upon bus speedMOTOROLA INC·Filed 1989·Granted Jul 12, 1994·11 cites·3 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →