System and method for protection against untrusted system management code by redirecting a system management interrupt and creating a virtual machine container

Abstract

A system and method for permitting the execution of system management mode (SMM) code during secure operations in a microprocessor system is described. In one embodiment, the system management interrupt (SMI) may be first directed to a handler in a secured virtual machine monitor (SVMM). The SMI may then be re-directed to SMM code located in a virtual machine (VM) that is under the security control of the SVMM. This redirection may be accomplished by allowing the SVMM to read and write the system management (SM) base register in the processor.

What is claimed is:  
     
         1 . A system, comprising: 
 a processor to operate in a user mode, a supervisor mode, and a sub operating system mode, to receive a sub operating system mode interrupt;    a first code to be contained within a first virtual machine; and    a first handler to be contained within a trusted code in a second virtual machine to redirect said sub operating system mode interrupt to said first code.    
     
     
         2 . The system of  claim 1 , wherein said trusted code is to write an interrupt service register in said processor.  
     
     
         3 . The system of  claim 2 , wherein said interrupt service register is a system management base register, and wherein said sub operating system mode interrupt is a system management interrupt.  
     
     
         4 . The system of  claim 1 , wherein said first code is to execute in page mode.  
     
     
         5 . The system of  claim 4 , wherein said first code is a system management mode code.  
     
     
         6 . The system of  claim 1 , further comprising a second handler within said trusted code to be invoked upon access attempts to locked pages of a memory.  
     
     
         7 . The system of  claim 6 , wherein said second handler determines if access is allowable to said locked pages of said memory.  
     
     
         8 . The system of  claim 6 , wherein said second handler initiates an exit from said first code by issuing a modified resume instruction.  
     
     
         9 . The system of  claim 8 , wherein said modified resume instruction is capable of execution in page mode.  
     
     
         10 . The system of  claim 1 , wherein said first handler establishes a space within locked pages of a memory to store state data.  
     
     
         11 . The system of  claim 1 , wherein said first code is located in unlocked pages of memory.  
     
     
         12 . The system of  claim 1 , wherein said system comprises a single processor system.  
     
     
         13 . The system of  claim 1 , wherein said trusted code is to disable an interrupt service register in said processor.  
     
     
         14 . The system of  claim 13 , wherein said interrupt service register is a system management base register, and wherein said first interrupt is a system management interrupt.  
     
     
         15 . The system of  claim 1 , wherein said first handler within said trusted code to be invoked upon access attempts to locked pages of a memory.  
     
     
         16 . The system of  claim 15 , wherein said first handler determines if access is allowable to said locked pages of said memory.  
     
     
         17 . The system of  claim 15 , wherein said first handler initiates an exit from said first code by issuing a modified resume instruction.  
     
     
         18 . The system of  claim 1 , wherein said modified resume instruction is capable of execution in page mode.  
     
     
         19 . A method, comprising: 
 directing a sub operating system mode interrupt to a first handler in a trusted code within a second virtual machine;    storing a state in a locked page in memory; and    entering a first code in a first virtual machine.    
     
     
         20 . The method of  claim 19 , further comprising invoking a second handler in said trusted code from said first code.  
     
     
         21 . The method of  claim 20 , wherein said invoking is subsequent to said first code accessing said locked page in memory.  
     
     
         22 . The method of  claim 19 , wherein said first code is system management mode code.  
     
     
         23 . The method of  claim 19 , further comprising invoking a second handler in said trusted code from said first code.  
     
     
         24 . The method of  claim 23 , wherein said invoking is subsequent to said first code accessing said locked page in memory.  
     
     
         25 . The method of  claim 19 , further comprising executing a modified resume instruction from a page mode.  
     
     
         26 . The method of  claim 19 , further comprising determining whether said first code may access said locked page in memory.  
     
     
         27 . The method of  claim 19 , wherein said directing includes writing a memory location within said trusted code to an interrupt service register.  
     
     
         28 . The method of  claim 27 , wherein said interrupt service register is a system management base register.  
     
     
         29 . The method of  claim 19 , wherein said sub operating system mode interrupt is a system management interrupt.  
     
     
         30 . The method of  claim 19 , further comprising invoking said first handler in said trusted code from said first code.  
     
     
         31 . The method of  claim 30 , wherein said invoking is subsequent to said first code accessing said locked page in memory.  
     
     
         32 . A processor, comprising 
 a first logic to execute a modified resume instruction; and    an interrupt service register capable of being written subsequent to execution of a secure enter instruction.    
     
     
         33 . The processor of  claim 32 , wherein said modified resume instruction returns said processor to previous program execution subsequent to execution of a first code.  
     
     
         34 . The processor of  claim 33 , wherein said modified resume instruction may be executed from within page mode.  
     
     
         35 . The processor of  claim 33 , wherein said execution of said first code occurs within a sub operating system mode.  
     
     
         36 . The processor of  claim 35 , wherein said sub operating system mode is a system management mode.  
     
     
         37 . The processor of  claim 32 , wherein said interrupt service register is a system management base register.  
     
     
         38 . A processor, comprising 
 a first logic to execute a modified resume instruction; and    an interrupt service register capable of being disabled subsequent to execution of a monitor initialization instruction.    
     
     
         39 . The processor of  claim 38 , wherein said modified resume instruction returns said processor to previous program execution subsequent to execution of a first code.  
     
     
         40 . The processor of  claim 39 , wherein said modified resume instruction may be executed from within page mode.  
     
     
         41 . The processor of  claim 39 , wherein said execution of said first code occurs within a sub operating system mode.  
     
     
         42 . The processor of  claim 41 , wherein said sub operating system mode is a system management mode.  
     
     
         43 . The processor of  claim 38 , wherein said interrupt service register is a system management base register.