Inventor · disambiguated record
Chung-Wah Norris Ip
Also filed as: IP CHUNG-WAH N · IP CHUNG-WAH NORRIS
30 granted patents·371 citations·filing 1999–2018
97Inventor score
Technology areasG06F
Files withCADENCE DESIGN SYSTEMS INC11JASPER DESIGN AUTOMATION INC10KRANEN KATHRYN DREWS3IP CHUNG-WAH NORRIS2JASPER DESIGN AUTOMATION2
Top patents by PatentIndex Score
30 records- 0190US7895552B1Extracting, visualizing, and acting on inconsistencies between a circuit design and its abstractionJASPER DESIGN AUTOMATION INC·Filed 2005·Granted Feb 22, 2011·30 cites·33 claims
- 0290US7159198B1System and method for identifying design efficiency and effectiveness parameters for verifying properties of a circuit modelJASPER DESIGN AUTOMATION·Filed 2003·Granted Jan 2, 2007·63 cites·66 claims
- 0388US8731894B1Indexing behaviors and recipes of a circuit designKRANEN KATHRYN DREWS·Filed 2012·Granted May 20, 2014·10 cites·20 claims
- 0488US8205187B1Generalizing and inferring behaviors of a circuit designCOELHO CLAUDIONOR JOSE NUNES·Filed 2010·Granted Jun 19, 2012·14 cites·20 claims
- 0587US8863049B1Constraining traces in formal verificationLUNDGREN LARS·Filed 2010·Granted Oct 14, 2014·16 cites·18 claims
- 0687US8630824B1Comprehending waveforms of a circuit designIP CHUNG-WAH NORRIS·Filed 2010·Granted Jan 14, 2014·13 cites·21 claims
- 0787US7437694B1System and method for determining and identifying signals that are relevantly determined by a selected signal in a circuit designJASPER DESIGN AUTOMATION·Filed 2005·Granted Oct 14, 2008·21 cites·19 claims
- 0885US8527911B1Comprehending a circuit designKRANEN KATHRYN DREWS·Filed 2010·Granted Sep 3, 2013·7 cites·16 claims
- 0984US10162917B1Method and system for implementing selective transformation for low power verificationCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Dec 25, 2018·5 cites·21 claims
- 1084US8984461B1Visualization constraints for circuit designsJASPER DESIGN AUTOMATION INC·Filed 2013·Granted Mar 17, 2015·7 cites·24 claims
- 1183US8990745B1Manipulation of traces for debugging behaviors of a circuit designJASPER DESIGN AUTOMATION INC·Filed 2013·Granted Mar 24, 2015·6 cites·20 claims
- 1283US8831925B1Indexing behaviors and recipes of a circuit designKRANEN KATHRYN DREWS·Filed 2010·Granted Sep 9, 2014·6 cites·18 claims
- 1383US7506288B1Interactive analysis and debugging of a circuit design during functional verification of the circuit designJASPER DESIGN AUTOMATION INC·Filed 2005·Granted Mar 17, 2009·13 cites·21 claims
- 1482US9659142B1Methods, systems, and articles of manufacture for trace warping for electronic designsCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted May 23, 2017·4 cites·20 claims
- 1582US9081927B2Manipulation of traces for debugging a circuit designJASPER DESIGN AUTOMATION INC·Filed 2013·Granted Jul 14, 2015·5 cites·20 claims
- 1682US7421668B1Meaningful visualization of properties independent of a circuit designJASPER DESIGN AUTOMATION INC·Filed 2004·Granted Sep 2, 2008·37 cites·55 claims
- 1782US7065726B1System and method for guiding and optimizing formal verification for a circuit designJASPER DESIGN AUTOMATION INC·Filed 2003·Granted Jun 20, 2006·36 cites·26 claims
- 1880US9734278B1Methods, systems, and articles of manufacture for automatic extraction of connectivity information for implementation of electronic designsCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Aug 15, 2017·6 cites·26 claims
- 1980US9477802B1Isolating differences between revisions of a circuit designIP CHUNG-WAH NORRIS·Filed 2010·Granted Oct 25, 2016·5 cites·24 claims
- 2080US7647572B1Managing formal verification complexity of designs with multiple related countersJASPER DESIGN AUTOMATION INC·Filed 2007·Granted Jan 12, 2010·9 cites·24 claims
- 2177US7418678B1Managing formal verification complexity of designs with countersJASPER DESIGN AUTOMATION INC·Filed 2004·Granted Aug 26, 2008·21 cites·29 claims
- 2275US10380295B1Methods, systems, and articles of manufacture for X-behavior verification of an electronic designCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Aug 13, 2019·2 cites·32 claims
- 2374US10094875B1Methods, systems, and articles of manufacture for graph-driven verification and debugging of an electronic designCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Oct 9, 2018·2 cites·24 claims
- 2468US7237208B1Managing formal verification complexity of designs with datapathsJASPER DESIGN AUTOMATION INC·Filed 2004·Granted Jun 26, 2007·14 cites·15 claims
- 2567US10635768B1System, method, and computer program product for displaying multiple traces while debugging during a formal verificationCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Apr 28, 2020·1 cites·20 claims
- 2661US9928328B1Method and system for automated debugging of a device under testCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Mar 27, 2018·1 cites·15 claims
- 2758US10409945B1Methods, systems, and computer program product for connectivity verification of electronic designsCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Sep 10, 2019·1 cites·24 claims
- 2850US10331547B1System, method, and computer program product for capture and reuse in a debug workspaceCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Jun 25, 2019·0 cites·20 claims
- 2946US10783304B1System, method, and computer program product for displaying debugging during a formal verificationCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Sep 22, 2020·0 cites·20 claims
- 3045US6915248B1Method and apparatus for transforming test stimulusCADENCE DESIGN SYSTEMS INC·Filed 1999·Granted Jul 5, 2005·16 cites·44 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →