Inventor · disambiguated record
Chingfu Lin
Also filed as: LIN CHINGFU
14 granted patents·3 pending applications·226 citations·filing 1998–2003
92Inventor score
Files withTAIWAN SEMICONDUCTOR MFG7TAIWAN SEMICONDUCTOR MFG CORP2UNITED MICROELECTRONICS CORP2WORLDWIDE SEMICONDUCTOR MFG2NOVELLUS SYSTEMS INC1
Top patents by PatentIndex Score
17 records- 0186US6261921B1Method of forming shallow trench isolation structureTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Jul 17, 2001·113 cites·20 claims
- 0278US7273808B1Reactive barrier/seed preclean process for damascene processNOVELLUS SYSTEMS INC·Filed 2003·Granted Sep 25, 2007·22 cites·12 claims
- 0360US6930038B2Dual damascene partial gap fill polymer fabrication processUNITED MICROELECTRONICS CORP·Filed 2001·Granted Aug 16, 2005·10 cites·16 claims
- 0458US6350681B1Method of forming dual damascene structureUNITED MICROELECTRONICS CORP·Filed 2001·Granted Feb 26, 2002·9 cites·18 claims
- 0555US6232184B1Method of manufacturing floating gate of stacked-gate nonvolatile memory unitTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted May 15, 2001·15 cites·22 claims
- 0654US6162679AMethod of manufacturing DRAM capacitorWORLDWIDE SEMICONDUCTOR MFG·Filed 1999·Granted Dec 19, 2000·19 cites·20 claims
- 0745US6277742B1Method of protecting tungsten plug from corrodingTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Aug 21, 2001·11 cites·14 claims
- 0840US2003199132A1Method for forming an opening in polymer-based dielectricFiled 2003·Application pending·0 cites
- 0939US2002177300A1Method for forming an opening in polymer-based dielectricFiled 2002·Application pending·0 cites
- 1038US6399506B2Method for planarizing an oxide layerTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Jun 4, 2002·7 cites·15 claims
- 1136US6221734B1Method of reducing CMP dishing effectTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Apr 24, 2001·6 cites·10 claims
- 1235US2002137305A1Fabrication method of shallow trench isolationFiled 2001·Application pending·0 cites
- 1334US6162732AMethod for reducing capacitance depletion during hemispherical grain polysilicon synthesis for DRAMTAIWAN SEMICONDUCTOR MFG CORP·Filed 1999·Granted Dec 19, 2000·3 cites·4 claims
- 1434US6159843AMethod of fabricating landing padWORLDWIDE SEMICONDUCTOR MFG·Filed 1999·Granted Dec 12, 2000·5 cites·8 claims
- 1533US6245667B1Method of forming viaTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Jun 12, 2001·3 cites·9 claims
- 1632US6207545B1Method for forming a T-shaped plug having increased contact areaTAIWAN SEMICONDUCTOR MFG CORP·Filed 1998·Granted Mar 27, 2001·3 cites·10 claims
- 1729US6277741B1Method and planarizing polysilicon layerTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Aug 21, 2001·0 cites·11 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →