Inventor · disambiguated record
Charan V. Surisetty
Also filed as: SURISETTY CHARAN V · SURISETTY CHARAN V V S · SURISETTY CHARAN VEERA VENKATA SATYA
82 granted patents·5 pending applications·382 citations·filing 2012–2025
99Inventor score
Top patents by PatentIndex Score
87 records- 0198US9443853B1Minimizing shorting between FinFET epitaxial regionsIBM·Filed 2015·Granted Sep 13, 2016·17 cites·16 claims
- 0298US9368512B1Double diamond shaped unmerged epitaxy for tall fins in tight pitchIBM·Filed 2015·Granted Jun 14, 2016·24 cites·20 claims
- 0398US9337094B1Method of forming contact useful in replacement metal gate processing and related semiconductor structureIBM·Filed 2015·Granted May 10, 2016·38 cites·19 claims
- 0497US9704753B2Minimizing shorting between FinFET epitaxial regionsIBM·Filed 2016·Granted Jul 11, 2017·10 cites·17 claims
- 0597US9397006B1Co-integration of different fin pitches for logic and analog devicesIBM·Filed 2015·Granted Jul 19, 2016·25 cites·20 claims
- 0696US10177240B2FinFET device formed by a replacement metal-gate method including a gate cut-last stepIBM·Filed 2015·Granted Jan 8, 2019·15 cites·3 claims
- 0796US9685340B2Stable contact on one-sided gate tie-down structureIBM·Filed 2015·Granted Jun 20, 2017·17 cites·17 claims
- 0896US9515073B1III-V semiconductor CMOS FinFET deviceIBM·Filed 2016·Granted Dec 6, 2016·12 cites·17 claims
- 0996US9431486B1Channel strain and controlling lateral epitaxial growth of the source and drain in FinFET devicesIBM·Filed 2015·Granted Aug 30, 2016·13 cites·20 claims
- 1095US9607898B1Simultaneously fabricating a high voltage transistor and a finFETIBM·Filed 2016·Granted Mar 28, 2017·9 cites·1 claims
- 1195US9595592B1Forming dual contact silicide using metal multi-layer and ion beam mixingIBM·Filed 2015·Granted Mar 14, 2017·11 cites·16 claims
- 1295US9305923B1Low resistance replacement metal gate structureIBM·Filed 2014·Granted Apr 5, 2016·18 cites·11 claims
- 1395US9059164B2Embedded interlevel dielectric barrier layers for replacement metal gate field effect transistorsIBM·Filed 2013·Granted Jun 16, 2015·19 cites·19 claims
- 1495US8728927B1Borderless contacts for semiconductor transistorsIBM·Filed 2012·Granted May 20, 2014·21 cites·25 claims
- 1594US9461168B1Channel strain and controlling lateral epitaxial growth of the source and drain in FinFET devicesIBM·Filed 2016·Granted Oct 4, 2016·8 cites·1 claims
- 1692US10256296B2Middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stackIBM·Filed 2015·Granted Apr 9, 2019·5 cites·11 claims
- 1792US9985024B2Minimizing shorting between FinFET epitaxial regionsIBM·Filed 2017·Granted May 29, 2018·4 cites·17 claims
- 1892US9887289B2Method and structure of improving contact resistance for passive and long channel devicesIBM·Filed 2015·Granted Feb 6, 2018·6 cites·9 claims
- 1992US9852951B2Minimizing shorting between FinFET epitaxial regionsIBM·Filed 2016·Granted Dec 26, 2017·4 cites·20 claims
- 2091US9871099B2Nanosheet isolation for bulk CMOS non-planar devicesIBM·Filed 2015·Granted Jan 16, 2018·6 cites·19 claims
- 2190US9647113B2Strained FinFET by epitaxial stressor independent of gate pitchIBM·Filed 2014·Granted May 9, 2017·6 cites·18 claims
- 2290US9601482B1Economical and environmentally friendly chemical mechanical polishing for III-V compound semiconductor device fabricationIBM·Filed 2015·Granted Mar 21, 2017·6 cites·20 claims
- 2390US9293576B2Semiconductor device with low-k gate cap and self-aligned contactIBM·Filed 2014·Granted Mar 22, 2016·9 cites·5 claims
- 2489US9728626B1Almost defect-free active channel regionGLOBALFOUNDRIES INC·Filed 2016·Granted Aug 8, 2017·5 cites·9 claims
- 2589US9704760B2Integrated circuit (IC) with offset gate sidewall contacts and method of manufactureIBM·Filed 2015·Granted Jul 11, 2017·6 cites·19 claims
- 2689US9520500B1Self heating reduction for analog radio frequency (RF) deviceIBM·Filed 2015·Granted Dec 13, 2016·5 cites·13 claims
- 2788US10355080B2Semiconductor structures including middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stackIBM·Filed 2016·Granted Jul 16, 2019·3 cites·6 claims
- 2888US9673101B2Minimize middle-of-line contact line shortsIBM·Filed 2015·Granted Jun 6, 2017·4 cites·17 claims
- 2987US11664375B2Minimizing shorting between FinFET epitaxial regionsTESSERA LLC·Filed 2021·Granted May 30, 2023·1 cites·20 claims
- 3087US10559530B2Forming dual metallization interconnect structures in single metallization levelIBM·Filed 2017·Granted Feb 11, 2020·4 cites·12 claims
- 3187US9275901B1Semiconductor device having reduced contact resistanceIBM·Filed 2014·Granted Mar 1, 2016·6 cites·10 claims
- 3286US10896816B2Silicon residue removal in nanosheet transistorsIBM·Filed 2017·Granted Jan 19, 2021·4 cites·20 claims
- 3386US9589827B2Shallow trench isolation regions made from crystalline oxidesIBM·Filed 2014·Granted Mar 7, 2017·6 cites·10 claims
- 3485US12237328B2Minimizing shorting between FinFET epitaxial regionsADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2023·Granted Feb 25, 2025·0 cites·16 claims
- 3584US12237368B2Semiconductor structures including middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stackADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2022·Granted Feb 25, 2025·0 cites·19 claims
- 3683US10347628B2Simultaneously fabricating a high voltage transistor and a FinFETIBM·Filed 2017·Granted Jul 9, 2019·2 cites·12 claims
- 3783US10043904B2Method and structure of improving contact resistance for passive and long channel devicesIBM·Filed 2017·Granted Aug 7, 2018·2 cites·1 claims
- 3882US10381458B2Semiconductor device replacement metal gate with gate cut last in RMGIBM·Filed 2015·Granted Aug 13, 2019·3 cites·11 claims
- 3982US10020306B2Spacer for trench epitaxial structuresIBM·Filed 2015·Granted Jul 10, 2018·2 cites·20 claims
- 4081US9905463B2Self-aligned low dielectric constant gate cap and a method of forming the sameIBM·Filed 2015·Granted Feb 27, 2018·2 cites·9 claims
- 4180US2025169171A1Minimizing shorting between finfet epitaxial regionsADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2025·Application pending·0 cites
- 4279US9564370B1Effective device formation for advanced technology nodes with aggressive fin-pitch scalingIBM·Filed 2015·Granted Feb 7, 2017·2 cites·10 claims
- 4379US9087796B2Semiconductor fabrication method using stop layerIBM·Filed 2013·Granted Jul 21, 2015·4 cites·14 claims
- 4478US9508816B2Low resistance replacement metal gate structureIBM·Filed 2016·Granted Nov 29, 2016·2 cites·9 claims
- 4577US10396200B2Method and structure of improving contact resistance for passive and long channel devicesIBM·Filed 2018·Granted Aug 27, 2019·1 cites·20 claims
- 4674US9905421B2Improving channel strain and controlling lateral epitaxial growth of the source and drain in FinFET devicesIBM·Filed 2016·Granted Feb 27, 2018·1 cites·20 claims
- 4773US11011429B2Minimize middle-of-line contact line shortsIBM·Filed 2020·Granted May 18, 2021·0 cites·6 claims
- 4873US10243044B2FinFETs with high quality source/drain structuresIBM·Filed 2017·Granted Mar 26, 2019·1 cites·17 claims
- 4973US9899378B2Simultaneously fabricating a high voltage transistor and a finFETIBM·Filed 2015·Granted Feb 20, 2018·1 cites·13 claims
- 5073US9406568B2Semiconductor structure containing low-resistance source and drain contactsIBM·Filed 2014·Granted Aug 2, 2016·2 cites·14 claims
Showing the top 50 of 87 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →