Inventor · disambiguated record
Daniel Chanemougame
Also filed as: CHANEMOUGAME DANIEL
102 granted patents·10 pending applications·734 citations·filing 2005–2025
99Inventor score
Files withTOKYO ELECTRON LTD46GLOBALFOUNDRIES INC42GLOBALFOUNDRIES US INC10IBM10CHANEMOUGAME DANIEL1
Top patents by PatentIndex Score
112 records- 0199US10510620B1Work function metal patterning for N-P space between active nanostructuresGLOBALFOUNDRIES INC·Filed 2018·Granted Dec 17, 2019·126 cites·6 claims
- 0299US10332803B1Hybrid gate-all-around (GAA) field effect transistor (FET) structure and method of formingGLOBALFOUNDRIES INC·Filed 2018·Granted Jun 25, 2019·83 cites·20 claims
- 0399US10192819B1Integrated circuit structure incorporating stacked field effect transistorsGLOBALFOUNDRIES INC·Filed 2017·Granted Jan 29, 2019·76 cites·20 claims
- 0499US10090193B1Integrated circuit structure incorporating a stacked pair of field effect transistors and a buried interconnect and methodGLOBALFOUNDRIES INC·Filed 2017·Granted Oct 2, 2018·68 cites·20 claims
- 0599US10026824B1Air-gap gate sidewall spacer and methodGLOBALFOUNDRIES INC·Filed 2017·Granted Jul 17, 2018·53 cites·17 claims
- 0698US10374040B1Method to form low resistance contactGLOBALFOUNDRIES INC·Filed 2018·Granted Aug 6, 2019·48 cites·18 claims
- 0797US12002869B2Gate contact structures and cross-coupled contact structures for transistor devicesGLOBALFOUNDRIES US INC·Filed 2022·Granted Jun 4, 2024·4 cites·16 claims
- 0897US11631671B23D complementary metal oxide semiconductor (CMOS) device and method of forming the sameTOKYO ELECTRON LTD·Filed 2020·Granted Apr 18, 2023·5 cites·23 claims
- 0997US11532708B2Stacked three-dimensional field-effect transistorsTOKYO ELECTRON LTD·Filed 2021·Granted Dec 20, 2022·5 cites·12 claims
- 1097US11264274B2Reverse contact and silicide process for three-dimensional logic devicesTOKYO ELECTRON LTD·Filed 2020·Granted Mar 1, 2022·5 cites·20 claims
- 1197US10304833B1Method of forming complementary nano-sheet/wire transistor devices with same depth contactsGLOBALFOUNDRIES INC·Filed 2018·Granted May 28, 2019·19 cites·20 claims
- 1297US10236215B1Methods of forming gate contact structures and cross-coupled contact structures for transistor devicesGLOBALFOUNDRIES INC·Filed 2017·Granted Mar 19, 2019·22 cites·19 claims
- 1396US11545497B2CFET SRAM bit cell with three stacked device decksTOKYO ELECTRON LTD·Filed 2020·Granted Jan 3, 2023·3 cites·18 claims
- 1496US10566248B1Work function metal patterning for N-P spaces between active nanostructures using unitary isolation pillarGLOBALFOUNDRIES INC·Filed 2018·Granted Feb 18, 2020·16 cites·6 claims
- 1596US10304832B1Integrated circuit structure incorporating stacked field effect transistors and methodGLOBALFOUNDRIES INC·Filed 2017·Granted May 28, 2019·16 cites·15 claims
- 1696US10170520B1Negative-capacitance steep-switch field effect transistor with integrated bi-stable resistive systemIBM·Filed 2018·Granted Jan 1, 2019·19 cites·20 claims
- 1796US9941162B1Self-aligned middle of the line (MOL) contactsGLOBALFOUNDRIES INC·Filed 2016·Granted Apr 10, 2018·13 cites·14 claims
- 1895US11201152B2Method, apparatus, and system for fin-over-nanosheet complementary field-effect-transistorGLOBALFOUNDRIES INC·Filed 2018·Granted Dec 14, 2021·12 cites·5 claims
- 1994US10692991B2Gate-all-around field effect transistors with air-gap inner spacers and methodsGLOBALFOUNDRIES INC·Filed 2018·Granted Jun 23, 2020·9 cites·7 claims
- 2094US9299721B2Method for making semiconductor device with different fin setsST MICROELECTRONICS INC·Filed 2014·Granted Mar 29, 2016·14 cites·26 claims
- 2193US12237333B2Power wall integration for multiple stacked devicesTOKYO ELECTRON LTD·Filed 2021·Granted Feb 25, 2025·2 cites·6 claims
- 2293US10388652B2Intergrated circuit structure including single diffusion break abutting end isolation region, and methods of forming sameGLOBALFOUNDRIES INC·Filed 2017·Granted Aug 20, 2019·10 cites·14 claims
- 2392US11923364B2Double cross-couple for two-row flip-flop using CFETTOKYO ELECTRON LTD·Filed 2021·Granted Mar 5, 2024·2 cites·20 claims
- 2492US11665878B2CFET SRAM bit cell with two stacked device decksTOKYO ELECTRON LTD·Filed 2021·Granted May 30, 2023·2 cites·20 claims
- 2592US10818792B2Nanosheet field-effect transistors formed with sacrificial spacersGLOBALFOUNDRIES INC·Filed 2018·Granted Oct 27, 2020·8 cites·12 claims
- 2692US10651284B2Methods of forming gate contact structures and cross-coupled contact structures for transistor devicesGLOBALFOUNDRIES INC·Filed 2017·Granted May 12, 2020·7 cites·18 claims
- 2792US10256316B1Steep-switch field effect transistor with integrated bi-stable resistive systemIBM·Filed 2018·Granted Apr 9, 2019·7 cites·9 claims
- 2892US10079173B2Methods of forming metallization lines on integrated circuit products and the resulting productsGLOBALFOUNDRIES INC·Filed 2016·Granted Sep 18, 2018·5 cites·22 claims
- 2991US11488947B2Highly regular logic design for efficient 3D integrationTOKYO ELECTRON LTD·Filed 2020·Granted Nov 1, 2022·2 cites·17 claims
- 3091US10685874B1Self-aligned cuts in an interconnect structureGLOBALFOUNDRIES INC·Filed 2018·Granted Jun 16, 2020·6 cites·17 claims
- 3191US10141446B2Formation of bottom junction in vertical FET devicesGLOBALFOUNDRIES INC·Filed 2017·Granted Nov 27, 2018·5 cites·13 claims
- 3290US11342427B23D directed self-assembly for nanostructuresTOKYO ELECTRON LTD·Filed 2020·Granted May 24, 2022·2 cites·20 claims
- 3390US11043418B2Middle of the line self-aligned direct pattern contactsGLOBALFOUNDRIES US INC·Filed 2019·Granted Jun 22, 2021·5 cites·19 claims
- 3489US12336274B2Self-aligned method for vertical recess for 3D device integrationTOKYO ELECTRON LTD·Filed 2022·Granted Jun 17, 2025·1 cites·20 claims
- 3589US11264289B2Method for threshold voltage tuning through selective deposition of high-K metal gate (HKMG) film stacksTOKYO ELECTRON LTD·Filed 2020·Granted Mar 1, 2022·2 cites·19 claims
- 3689US11233006B2Metallization lines on integrated circuit productsGLOBALFOUNDRIES US INC·Filed 2018·Granted Jan 25, 2022·3 cites·20 claims
- 3789US10290549B2Integrated circuit structure, gate all-around integrated circuit structure and methods of forming sameGLOBALFOUNDRIES INC·Filed 2017·Granted May 14, 2019·6 cites·7 claims
- 3888US11574845B2Apparatus and method for simultaneous formation of diffusion break, gate cut, and independent N and P gates for 3D transistor devicesTOKYO ELECTRON LTD·Filed 2020·Granted Feb 7, 2023·2 cites·13 claims
- 3988US11177250B2Method for fabrication of high density logic and memory for advanced circuit architectureTOKYO ELECTRON LTD·Filed 2020·Granted Nov 16, 2021·2 cites·20 claims
- 4088US2024413082A1Metallization lines on integrated circuit productsGLOBALFOUNDRIES US INC·Filed 2024·Application pending·0 cites
- 4187US10347745B2Methods of forming bottom and top source/drain regions on a vertical transistor deviceGLOBALFOUNDRIES INC·Filed 2016·Granted Jul 9, 2019·5 cites·17 claims
- 4287US9842933B1Formation of bottom junction in vertical FET devicesGLOBALFOUNDRIES INC·Filed 2016·Granted Dec 12, 2017·4 cites·14 claims
- 4386US11764113B2Method of 3D logic fabrication to sequentially decrease processing temperature and maintain material thermal thresholdsTOKYO ELECTRON LTD·Filed 2021·Granted Sep 19, 2023·1 cites·20 claims
- 4486US11723187B2Three-dimensional memory cell structureTOKYO ELECTRON LTD·Filed 2021·Granted Aug 8, 2023·1 cites·20 claims
- 4585US12131994B2Metallization lines on integrated circuit productsGLOBALFOUNDRIES US INC·Filed 2023·Granted Oct 29, 2024·0 cites·19 claims
- 4685US11646318B2Connections from buried interconnects to device terminals in multiple stacked devices structuresTOKYO ELECTRON LTD·Filed 2021·Granted May 9, 2023·1 cites·7 claims
- 4784US11581242B2Integrated high efficiency gate on gate coolingTOKYO ELECTRON LTD·Filed 2021·Granted Feb 14, 2023·1 cites·14 claims
- 4884US10950610B2Asymmetric gate cut isolation for SRAMGLOBALFOUNDRIES US INC·Filed 2019·Granted Mar 16, 2021·3 cites·10 claims
- 4984US10249728B2Air-gap gate sidewall spacer and methodGLOBALFOUNDRIES INC·Filed 2018·Granted Apr 2, 2019·3 cites·18 claims
- 5084US10074564B2Self-aligned middle of the line (MOL) contactsGLOBALFOUNDRIES INC·Filed 2018·Granted Sep 11, 2018·3 cites·18 claims
Showing the top 50 of 112 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →