Inventor · disambiguated record
Daesik Choi
Also filed as: CHOI DAESIK
81 granted patents·12 pending applications·1,115 citations·filing 2006–2017
99Inventor score
Top patents by PatentIndex Score
93 records- 0198US8895440B2Semiconductor die and method of forming Fo-WLCSP vertical interconnect using TSV and TMVCHOI DAESIK·Filed 2010·Granted Nov 25, 2014·81 cites·23 claims
- 0298US8476115B2Semiconductor device and method of mounting cover to semiconductor die and interposer with adhesive materialCHOI DAESIK·Filed 2011·Granted Jul 2, 2013·47 cites·32 claims
- 0398US8232141B2Integrated circuit packaging system with conductive pillars and method of manufacture thereofCHOI DAESIK·Filed 2011·Granted Jul 31, 2012·114 cites·11 claims
- 0498US8008121B2Semiconductor package and method of mounting semiconductor die to opposite sides of TSV substrateSTATS CHIPPAC LTD·Filed 2009·Granted Aug 30, 2011·105 cites·13 claims
- 0597US8063475B2Semiconductor package system with through silicon via interposerCHOI DAESIK·Filed 2008·Granted Nov 22, 2011·56 cites·18 claims
- 0697US7923304B2Integrated circuit packaging system with conductive pillars and method of manufacture thereofSTATS CHIPPAC LTD·Filed 2009·Granted Apr 12, 2011·61 cites·4 claims
- 0796US8502387B2Integrated circuit packaging system with vertical interconnection and method of manufacture thereofCHOI DAESIK·Filed 2010·Granted Aug 6, 2013·48 cites·20 claims
- 0896US8263435B2Semiconductor device and method of stacking semiconductor die in mold laser package interconnected by bumps and conductive viasCHOI DAESIK·Filed 2010·Granted Sep 11, 2012·47 cites·25 claims
- 0995US8409979B2Semiconductor device and method of forming interconnect structure with conductive pads having expanded interconnect surface area for enhanced interconnection propertiesCHOI DAESIK·Filed 2011·Granted Apr 2, 2013·17 cites·17 claims
- 1095US8168317B2Battery module of improved safety and middle or large-sized battery pack containing the sameYOON HEE SOO·Filed 2011·Granted May 1, 2012·18 cites·10 claims
- 1194US7779467B2N grouping of traffic and pattern-free internet worm response system and method using N grouping of trafficKOREA ELECTRONICS TELECOMM·Filed 2006·Granted Aug 17, 2010·167 cites·6 claims
- 1293US8941225B2Integrated circuit package and method for manufacturing the sameSTS SC & TELECOMM CO LTD·Filed 2013·Granted Jan 27, 2015·18 cites·10 claims
- 1392US9378983B2Semiconductor device and method of mounting cover to semiconductor die and interposer with adhesive materialSTATS CHIPPAC LTD·Filed 2013·Granted Jun 28, 2016·13 cites·30 claims
- 1491US9153494B2Semiconductor die and method of forming Fo-WLCSP vertical interconnect using TSV and TMVSTATS CHIPPAC LTD·Filed 2013·Granted Oct 6, 2015·9 cites·42 claims
- 1591US8409923B2Integrated circuit packaging system with underfill and method of manufacture thereofKIM OH HAN·Filed 2011·Granted Apr 2, 2013·15 cites·20 claims
- 1691US8273604B2Semiconductor device and method of forming WLCSP structure using protruded MLPKIM OHHAN·Filed 2011·Granted Sep 25, 2012·17 cites·22 claims
- 1790US9190297B2Semiconductor device and method of forming a stackable semiconductor package with vertically-oriented discrete electrical devices as interconnect structuresCHOI DAESIK·Filed 2011·Granted Nov 17, 2015·14 cites·36 claims
- 1890US8642381B2Semiconductor device and method of forming protective layer over exposed surfaces of semiconductor diePAGAILA REZA A·Filed 2010·Granted Feb 4, 2014·10 cites·24 claims
- 1990US8519544B2Semiconductor device and method of forming WLCSP structure using protruded MLPKIM OHHAN·Filed 2012·Granted Aug 27, 2013·13 cites·25 claims
- 2090US8288203B2Semiconductor device and method of forming a wafer level package structure using conductive via and exposed bumpCHO SUNGWON·Filed 2011·Granted Oct 16, 2012·12 cites·20 claims
- 2189US8648469B2Semiconductor package and method of mounting semiconductor die to opposite sides of TSV substrateCHOI DAESIK·Filed 2011·Granted Feb 11, 2014·8 cites·26 claims
- 2289US8273607B2Integrated circuit packaging system with encapsulation and underfill and method of manufacture thereofPARK SOO-SAN·Filed 2010·Granted Sep 25, 2012·11 cites·16 claims
- 2388US9252094B2Semiconductor device and method of forming an interconnect structure with conductive material recessed within conductive ring over surface of conductive pillarCHOI DAESIK·Filed 2011·Granted Feb 2, 2016·10 cites·17 claims
- 2488US9142515B2Semiconductor device with protective layer over exposed surfaces of semiconductor dieSTATS CHIPPAC LTD·Filed 2013·Granted Sep 22, 2015·7 cites·25 claims
- 2588US8709935B2Semiconductor device and method of forming interconnect structure with conductive pads having expanded interconnect surface area for enhanced interconnection propertiesSTATS CHIPPAC LTD·Filed 2013·Granted Apr 29, 2014·7 cites·21 claims
- 2687US9373578B2Semiconductor device and method of forming interconnect structure with conductive pads having expanded interconnect surface area for enhanced interconnection propertiesSTATS CHIPPAC LTD·Filed 2014·Granted Jun 21, 2016·6 cites·26 claims
- 2786US10665534B2Semiconductor device and method of using partial wafer singulation for improved wafer level embedded system in packageSTATS CHIPPAC PTE LTD·Filed 2017·Granted May 26, 2020·5 cites·18 claims
- 2886US8466567B2Integrated circuit packaging system with stack interconnect and method of manufacture thereofCHOI DAESIK·Filed 2010·Granted Jun 18, 2013·9 cites·14 claims
- 2985US8574964B2Semiconductor device and method of forming electrical interconnection between semiconductor die and substrate with continuous body of solder tapeCHO SUNGWON·Filed 2010·Granted Nov 5, 2013·7 cites·25 claims
- 3085US7943252B2Battery module of improved safety and middle or large-sized battery pack containing the sameLG CHEMICAL LTD·Filed 2008·Granted May 17, 2011·5 cites·9 claims
- 3184US9312218B2Semiconductor device and method of forming leadframe with conductive bodies for vertical electrical interconnect of semiconductor dieCHOI DAESIK·Filed 2011·Granted Apr 12, 2016·8 cites·20 claims
- 3284US8519536B2Semiconductor device including bump formed on substrate to prevent extremely-low dielectric constant (ELK) interlayer dielectric layer (ILD) delamination during reflow processSTATS CHIPPAC LTD·Filed 2012·Granted Aug 27, 2013·5 cites·25 claims
- 3384US8405197B2Integrated circuit packaging system with stacked configuration and method of manufacture thereofHA JONG-WOO·Filed 2009·Granted Mar 26, 2013·12 cites·20 claims
- 3484US7872340B2Integrated circuit package system employing an offset stacked configurationSTATS CHIPPAC LTD·Filed 2008·Granted Jan 18, 2011·10 cites·18 claims
- 3583US9281228B2Semiconductor device and method of forming thermal interface material and heat spreader over semiconductor dieCHOI DAESIK·Filed 2011·Granted Mar 8, 2016·7 cites·32 claims
- 3683US9252032B2Semiconductor device and method of stacking semiconductor die in mold laser package interconnected by bumps and conductive viasCHOI DAESIK·Filed 2012·Granted Feb 2, 2016·6 cites·31 claims
- 3783US8698297B2Integrated circuit packaging system with stack deviceBAE JOHYUN·Filed 2011·Granted Apr 15, 2014·6 cites·4 claims
- 3883US8367467B2Semiconductor method of forming bump on substrate to prevent ELK ILD delamination during reflow processSTATS CHIPPAC LTD·Filed 2010·Granted Feb 5, 2013·5 cites·25 claims
- 3982US9305897B2Semiconductor package and method of mounting semiconductor die to opposite sides of TSV substrateSTATS CHIPPAC LTD·Filed 2013·Granted Apr 5, 2016·4 cites·24 claims
- 4081US8710670B2Integrated circuit packaging system with coupling features and method of manufacture thereofKIM MINJUNG·Filed 2011·Granted Apr 29, 2014·7 cites·20 claims
- 4180US8559185B2Integrated circuit package system with stackable devices and a method of manufacture thereofLEE SANG-HO·Filed 2012·Granted Oct 15, 2013·4 cites·20 claims
- 4279US8723310B2Integrated circuit packaging system having warpage prevention structuresPARK YISU·Filed 2012·Granted May 13, 2014·8 cites·10 claims
- 4379US8679900B2Integrated circuit packaging system with heat conduction and method of manufacture thereofCHOI DAESIK·Filed 2011·Granted Mar 25, 2014·6 cites·2 claims
- 4479US8546194B2Integrated circuit packaging system with interconnects and method of manufacture thereofCHOI JOONYOUNG·Filed 2011·Granted Oct 1, 2013·6 cites·20 claims
- 4579US8518752B2Integrated circuit packaging system with stackable package and method of manufacture thereofYANG DEOKKYUNG·Filed 2009·Granted Aug 27, 2013·8 cites·20 claims
- 4679US8383458B2Integrated circuit package system employing an offset stacked configuration and method for manufacturing thereofSTATS CHIPPAC LTD·Filed 2010·Granted Feb 26, 2013·4 cites·15 claims
- 4778US8710640B2Integrated circuit packaging system with heat slug and method of manufacture thereofCHOI DAESIK·Filed 2011·Granted Apr 29, 2014·5 cites·18 claims
- 4878US8189344B2Integrated circuit package system for stackable devicesLEE SANG-HO·Filed 2008·Granted May 29, 2012·6 cites·18 claims
- 4977US10068877B2Semiconductor device and method of forming WLCSP with semiconductor die embedded within interconnect structureSTATS CHIPPAC LTD·Filed 2016·Granted Sep 4, 2018·3 cites·7 claims
- 5077US9406579B2Semiconductor device and method of controlling warpage in semiconductor packageCHOI DAESIK·Filed 2012·Granted Aug 2, 2016·5 cites·27 claims
Showing the top 50 of 93 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →