Inventor · disambiguated record
David E. Eichstadt
Also filed as: EICHSTADT DAVID E · EICHSTADT DAVID ELY
13 granted patents·5 pending applications·75 citations·filing 2000–2024
90Inventor score
Top patents by PatentIndex Score
18 records- 0187US12031851B2Actuator apparatus with light actuated position sensor and secure position verificationDTL LINEAR LLC·Filed 2023·Granted Jul 9, 2024·3 cites·20 claims
- 0283US6468413B1Electrochemical etch for high tin solder bumpsIBM·Filed 2000·Granted Oct 22, 2002·19 cites·21 claims
- 0382US7144490B2Method for selective electroplating of semiconductor device I/O pads using a titanium-tungsten seed layerIBM·Filed 2003·Granted Dec 5, 2006·14 cites·7 claims
- 0481US7566649B2Compressible films surrounding solder connectorsIBM·Filed 2007·Granted Jul 28, 2009·8 cites·19 claims
- 0576US12416513B2Actuator apparatus with light actuated position sensor and secure position verificationDTL LINEAR LLC·Filed 2024·Granted Sep 16, 2025·0 cites·16 claims
- 0676US7316572B2Compliant electrical contactsIBM·Filed 2005·Granted Jan 8, 2008·6 cites·14 claims
- 0772US7473997B2Method for forming robust solder interconnect structures by reducing effects of seed layer underetchingIBM·Filed 2005·Granted Jan 6, 2009·4 cites·10 claims
- 0862US6995475B2I/C chip suitable for wire bondingIBM·Filed 2003·Granted Feb 7, 2006·9 cites·3 claims
- 0958US7332821B2Compressible films surrounding solder connectorsIBM·Filed 2004·Granted Feb 19, 2008·7 cites·21 claims
- 1050US6992389B2Barrier for interconnect and methodIBM·Filed 2004·Granted Jan 31, 2006·4 cites·10 claims
- 1147US2008000080A1Compliant electrical contactsBERNIER WILLIAM E·Filed 2007·Application pending·0 cites
- 1246US7572726B2Method of forming a bond pad on an I/C chip and resulting structureIBM·Filed 2005·Granted Aug 11, 2009·0 cites·15 claims
- 1346US2006249854A1Device with area array pads for test probingCHENG TIEN-JEN·Filed 2006·Application pending·0 cites
- 1445US7767575B2Forming robust solder interconnect structures by reducing effects of seed layer underetchingTESSERA INTELLECTUAL PROPERTIE·Filed 2009·Granted Aug 3, 2010·0 cites·5 claims
- 1541US6900142B2Inhibition of tin oxide formation in lead free interconnect formationIBM·Filed 2003·Granted May 31, 2005·1 cites·9 claims
- 1640US2005167837A1Device with area array pads for test probingIBM·Filed 2004·Application pending·0 cites
- 1739US2005026416A1Encapsulated pin structure for improved reliability of waferIBM·Filed 2003·Application pending·0 cites
- 1837US2005104208A1Stabilizing copper overlayer for enhanced c4 interconnect reliabilityIBM·Filed 2003·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →