Inventor · disambiguated record
David Pritchard
Also filed as: PRITCHARD DAVID · PRITCHARD DAVID C · PRITCHARD David Charles
43 granted patents·17 pending applications·126 citations·filing 2001–2025
96Inventor score
Top patents by PatentIndex Score
60 records- 0191US9224617B2Forming cross-coupled line segmentsGLOBALFOUNDRIES INC·Filed 2014·Granted Dec 29, 2015·13 cites·18 claims
- 0290US11610843B2Well tap for an integrated circuit product and methods of forming such a well tapGLOBALFOUNDRIES US INC·Filed 2021·Granted Mar 21, 2023·2 cites·13 claims
- 0388US10529704B1Auxiliary gate antenna diodesGLOBALFOUNDRIES INC·Filed 2018·Granted Jan 7, 2020·7 cites·20 claims
- 0486US11226231B1Image sensor incorporating an array of optically switchable magnetic tunnel junctionsGLOBALFOUNDRIES US INC·Filed 2020·Granted Jan 18, 2022·2 cites·20 claims
- 0586US6562700B1Process for removal of resist mask over low k carbon-doped silicon oxide dielectric material of an integrated circuit structure, and removal of residues from via etch and resist mask removalLSI LOGIC CORP·Filed 2001·Granted May 13, 2003·57 cites·28 claims
- 0684US10068806B2Method, apparatus, and system for using a cover mask for enabling metal line jumping over MOL features in a standard cellGLOBALFOUNDRIES INC·Filed 2018·Granted Sep 4, 2018·3 cites·10 claims
- 0783US9947590B1Method, apparatus, and system for using a cover mask for enabling metal line jumping over MOL features in a standard cellGLOBALFOUNDRIES INC·Filed 2016·Granted Apr 17, 2018·3 cites·13 claims
- 0882US10347543B2FDSOI semiconductor device with contact enhancement layer and method of manufacturingGLOBALFOUNDRIES INC·Filed 2017·Granted Jul 9, 2019·4 cites·19 claims
- 0981US7955919B2Spacer-less transistor integration scheme for high-K gate dielectrics and small gate-to-gate spaces applicable to Si, SiGe and strained silicon schemesLSI CORP·Filed 2007·Granted Jun 7, 2011·8 cites·21 claims
- 1077US10727108B2Dummy gate isolation and method of production thereofGLOBALFOUNDRIES INC·Filed 2018·Granted Jul 28, 2020·2 cites·5 claims
- 1176US11276651B2IC product comprising a single active fin FinFET device and an electrically inactive fin stress reduction structureGLOBALFOUNDRIES US INC·Filed 2020·Granted Mar 15, 2022·1 cites·17 claims
- 1276US11177182B2Vertical transistor device comprising a two-dimensional (2D) material positioned in a channel region of the device and methods of making such vertical transistor devicesGLOBALFOUNDRIES US INC·Filed 2020·Granted Nov 16, 2021·1 cites·18 claims
- 1374US10262941B2Devices and methods for forming cross coupled contactsGLOBALFOUNDRIES INC·Filed 2016·Granted Apr 16, 2019·2 cites·13 claims
- 1472US9465907B2Multi-polygon constraint decomposition techniques for use in double patterning applicationsGLOBALFOUNDRIES INC·Filed 2014·Granted Oct 11, 2016·3 cites·20 claims
- 1568US9472455B2Methods of cross-coupling line segments on a waferGLOBALFOUNDRIES INC·Filed 2014·Granted Oct 18, 2016·2 cites·20 claims
- 1667US12457799B2Antenna structureGLOBALFOUNDRIES US INC·Filed 2023·Granted Oct 28, 2025·0 cites·17 claims
- 1766US12364000B1Device structures for a high-voltage semiconductor deviceGLOBALFOUNDRIES US INC·Filed 2024·Granted Jul 15, 2025·0 cites·19 claims
- 1865US12356675B2Planar transistor device comprising at least one layer of a two-dimensional (2D) materialGLOBALFOUNDRIES US INC·Filed 2023·Granted Jul 8, 2025·0 cites·19 claims
- 1964US7361965B2Method and apparatus for redirecting void diffusion away from vias in an integrated circuit designLSI LOGIC CORP·Filed 2005·Granted Apr 22, 2008·2 cites·18 claims
- 2062US12501624B1Memory device structures that include a capacitorGLOBALFOUNDRIES US INC·Filed 2024·Granted Dec 16, 2025·0 cites·20 claims
- 2162US12464784B2Isolation structures of semiconductor devicesGLOBALFOUNDRIES US INC·Filed 2022·Granted Nov 4, 2025·0 cites·19 claims
- 2262US11913971B2Motion-sensitive field effect transistor, motion detection system, and methodGLOBALFOUNDRIES US INC·Filed 2021·Granted Feb 27, 2024·0 cites·20 claims
- 2362US11239087B2Fully depleted devices with slots in active regionsGLOBALFOUNDRIES US INC·Filed 2019·Granted Feb 1, 2022·0 cites·14 claims
- 2462US8018070B2Semiconductor device, method for manufacturing semiconductor devices and mask systems used in the manufacturing of semiconductor devicesQIMONDA AG·Filed 2007·Granted Sep 13, 2011·4 cites·23 claims
- 2562US7436040B2Method and apparatus for diverting void diffusion in integrated circuit conductorsLSI CORP·Filed 2005·Granted Oct 14, 2008·2 cites·13 claims
- 2662US2024387668A1Nanosheet structures with tunable channels and inner sidewall spacersGLOBALFOUNDRIES US INC·Filed 2023·Application pending·0 cites
- 2761US12513995B2Substrates of semiconductor devices having varying thicknesses of semiconductor layersGLOBALFOUNDRIES US INC·Filed 2022·Granted Dec 30, 2025·0 cites·13 claims
- 2861US12424493B2Self-aligned double patterning with mandrel manipulationGLOBALFOUNDRIES US INC·Filed 2022·Granted Sep 23, 2025·0 cites·20 claims
- 2960US12464745B2Bipolar junction transistor arraysGLOBALFOUNDRIES US INC·Filed 2022·Granted Nov 4, 2025·0 cites·20 claims
- 3058US10497576B1Devices with slotted active regionsGLOBALFOUNDRIES INC·Filed 2018·Granted Dec 3, 2019·0 cites·11 claims
- 3157US7678654B2Buried bitline with reduced resistanceQIMONDA AG·Filed 2006·Granted Mar 16, 2010·2 cites·7 claims
- 3256US10186524B2Fully depleted silicon-on-insulator (FDSOI) transistor device and self-aligned active area in FDSOI bulk exposed regionsGLOBALFOUNDRIES INC·Filed 2018·Granted Jan 22, 2019·0 cites·20 claims
- 3356US8021933B2Integrated circuit including structures arranged at different densities and method of forming the sameQIMONDA AG·Filed 2007·Granted Sep 20, 2011·1 cites·16 claims
- 3456US2025254985A1Finfet with gate-all-around structure including gate dielectric layer thicker in buried gate region than in outer gate regionGLOBALFOUNDRIES US INC·Filed 2024·Application pending·0 cites
- 3554US11581430B2Planar transistor device comprising at least one layer of a two-dimensional (2D) material and methods for making such transistor devicesGLOBALFOUNDRIES US INC·Filed 2019·Granted Feb 14, 2023·0 cites·21 claims
- 3654US2025203937A1Nanosheet devices with reduced width inner spacer and methodGLOBALFOUNDRIES US INC·Filed 2023·Application pending·0 cites
- 3754US2025245410A1Method and system employing linear distance marker-based design layout analysisGLOBALFOUNDRIES US INC·Filed 2024·Application pending·0 cites
- 3854US2025241062A1Structure with two work function metals over conductive bridge, and method to form sameGLOBALFOUNDRIES US INC·Filed 2024·Application pending·0 cites
- 3953US7582566B2Method for redirecting void diffusion away from vias in an integrated circuit designLSI LOGIC CORP·Filed 2008·Granted Sep 1, 2009·0 cites·11 claims
- 4053US2025040167A1Gate-all-around field effect transistorsGLOBALFOUNDRIES US INC·Filed 2023·Application pending·0 cites
- 4153US2024274603A1Standard cell and ic structure with trench isolation through active regions and gate electrodesGLOBALFOUNDRIES US INC·Filed 2023·Application pending·0 cites
- 4253US2024234448A1Lateral capacitors of semiconductor devicesGLOBALFOUNDRIES US INC·Filed 2023·Application pending·0 cites
- 4352US2025031439A1Fin-type field effect transistor with independently biasable supplementary gate and methodGLOBALFOUNDRIES US INC·Filed 2023·Application pending·0 cites
- 4452US2025173495A1Real-time process margin-based layout optimizationGLOBALFOUNDRIES US INC·Filed 2023·Application pending·0 cites
- 4551US2024347638A1Multi-fin fin-type field effect transistor with fine-tuned effective channel widthGLOBALFOUNDRIES US INC·Filed 2023·Application pending·0 cites
- 4650US9941301B1Fully depleted silicon-on-insulator (FDSOI) transistor device and self-aligned active area in FDSOI bulk exposed regionsGLOBALFOUNDRIES INC·Filed 2016·Granted Apr 10, 2018·0 cites·12 claims
- 4750US9436081B2Methods of modifying masking reticles to remove forbidden pitch regions thereofGLOBALFOUNDRIES INC·Filed 2014·Granted Sep 6, 2016·0 cites·20 claims
- 4850US7259083B2Local interconnect manufacturing processLSI CORP·Filed 2004·Granted Aug 21, 2007·5 cites·10 claims
- 4949US11722298B2Public-private encryption key generation using Pcell parameter values and on-chip physically unclonable function valuesGLOBALFOUNDRIES US INC·Filed 2020·Granted Aug 8, 2023·0 cites·20 claims
- 5048US11094791B1Vertical transistor device with source/drain regions comprising a twi-dimensional (2D) material and methods of making such vertical transistor devicesGLOBALFOUNDRIES US INC·Filed 2020·Granted Aug 17, 2021·0 cites·20 claims
Showing the top 50 of 60 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →