Methods of cross-coupling line segments on a wafer

Abstract

A method is provided for fabricating cross-coupled line segments on a wafer for use, for instance, in fabricating cross-coupled gates of two or more transistors. The fabricating includes: patterning a first line segment with a first side projection using a first mask; and patterning a second line segment with a second side projection using a second mask. The second line segment is offset from the first line segment, and the patterned second side projection overlies the patterned first side projection, and facilitates defining a cross-stitch segment connecting the first and second line segments. The method further includes selectively cutting the first and second line segments in defining the cross-coupled line segments from the first and second line segments and the cross-stitch segment.

What is claimed is: 
     
       1. A method comprising:
 fabricating a structure comprising cross-coupled line segments on a wafer, the fabricating comprising:
 patterning a first line segment with a first side projection therefrom using a first mask; 
 after pattering the first line segment, patterning a second line segment with a second side projection therefrom using a second mask, the second line segment being offset from the first line segment, and the patterned second side projection overlying the patterned first side projection and facilitating defining a cross-stitch segment connecting the first and second line segments; and 
 selectively cutting the first and second line segments to define the cross-coupled line segments from the first and second line segments and the cross-stitch segment. 
 
 
     
     
       2. The method of  claim 1 , wherein patterning the first line segment comprises a first lithographic patterning of at least one first layer on the wafer to facilitate defining the first line segment with the first side projection therefrom on the wafer. 
     
     
       3. The method of  claim 2 , wherein patterning the first line segment comprises performing at least one first etching of the at least the first layer to pattern the first line segment with the first side projection therein. 
     
     
       4. The method of  claim 3 , wherein patterning the second line segment comprises a second lithographic patterning of at least one second layer on the wafer to facilitate defining the second line segment with the second side projection therefrom on the wafer. 
     
     
       5. The method of  claim 4 , wherein patterning the second line segment comprises performing at least one second etching of the at least one second layer to pattern the second line segment with the second side projection therein. 
     
     
       6. The method of  claim 5 , further comprising performing at least one further etch process to define the first and second line segments and the cross-stitch segment in at least one common layer on the wafer. 
     
     
       7. The method of  claim 6 , wherein the selectively cutting comprises selectively cutting the first and second line segments in the at least one common layer on the wafer in defining the cross-coupled line segments from the first and second line segments and the cross-stitch segment. 
     
     
       8. The method of  claim 6 , wherein the at least one common layer of the wafer comprises at least one sacrificial gate layer on the wafer, the at least one sacrificial gate layer facilitating forming sacrificial gates for a plurality of transistors of the structure. 
     
     
       9. The method of  claim 1 , wherein patterning the first line segment comprises a first lithographic patterning of at least one first layer on a wafer to facilitate defining the first line segment with the first side projection therefrom on the wafer, and patterning the second line segment comprises a second lithographic patterning of at least one second layer on the wafer to facilitate defining the second line segment with the second side projection therefrom on the wafer. 
     
     
       10. The method of  claim 9 , further comprising performing at least one further etch process to define the first and second line segments and the cross-stitch segment in at least one common layer on the wafer. 
     
     
       11. The method of  claim 10 , wherein the selectively cutting comprises selectively cutting the first and second line segments in the at least one common layer on the wafer in defining the cross-coupled line segments from the first and second line segments in the cross-stitch segment. 
     
     
       12. The method of  claim 1 , wherein the fabricating comprises providing the cross-stitch segment co-planar with the first and second line segments. 
     
     
       13. The method of  claim 1 , wherein the patterned first side projection from the first line segment and the patterned second side projection from the second line segment are mirror image projections. 
     
     
       14. The method of  claim 1 , wherein the cross-stitch segment has a transverse width larger than a transverse width of the first line segment or a transverse width of the second line segment. 
     
     
       15. The method of  claim 1 , wherein the cross-stitch segment is co-planar with, and a rectangular-shaped interconnection between, the first and second line segments. 
     
     
       16. The method of  claim 1 , wherein the cross-stitch segment extends orthogonal from the first line segment and extends orthogonal from the second line segment. 
     
     
       17. The method of  claim 1 , wherein the fabricating comprises etching the first line segment, the second line segment, and the cross-stitch segment into at least one common layer on the wafer. 
     
     
       18. The method of  claim 17 , wherein the at least one common layer of the wafer comprises a sacrificial gate layer. 
     
     
       19. The method of  claim 17 , wherein the selectively cutting comprises selectively cutting the first and second line segments in the at least one common layer on the wafer via at least one cut mask to define the cross-coupled line segments from the first and second line segments and the cross-stitch segment. 
     
     
       20. The method of  claim 1 , wherein the fabricating further comprises forming a plurality of transistors, and wherein the cross-coupled line segments facilitate forming cross-coupled gates of multiple transistors of the plurality of transistors.