Inventor · disambiguated record
Jason E. Stephens
Also filed as: STEPHENS JASON · STEPHENS JASON E · STEPHENS JASON EUGENE
40 granted patents·2 pending applications·286 citations·filing 2012–2022
97Inventor score
Files withGLOBALFOUNDRIES INC36GLOBALFOUNDRIES US INC2RASHED MAHBUB1STEPHENS JASON E1STEPHENS JASON EUGENE1
Top patents by PatentIndex Score
42 records- 0198US9818641B1Apparatus and method of forming self-aligned cuts in mandrel and a non-mandrel lines of an array of metal linesGLOBALFOUNDRIES INC·Filed 2016·Granted Nov 14, 2017·32 cites·16 claims
- 0297US9852986B1Method of patterning pillars to form variable continuity cuts in interconnection lines of an integrated circuitGLOBALFOUNDRIES INC·Filed 2016·Granted Dec 26, 2017·19 cites·10 claims
- 0397US9818640B1Apparatus and method of forming self-aligned cuts in a non-mandrel line of an array of metal linesGLOBALFOUNDRIES INC·Filed 2016·Granted Nov 14, 2017·19 cites·16 claims
- 0495US9818651B2Methods, apparatus and system for a passthrough-based architectureGLOBALFOUNDRIES INC·Filed 2016·Granted Nov 14, 2017·15 cites·10 claims
- 0595US8969199B1Methods of forming a circuit that includes a cross-coupling gate contact structure wherein the circuit is to be manufactured using a triple patterning processGLOBALFOUNDRIES INC·Filed 2013·Granted Mar 3, 2015·25 cites·19 claims
- 0694US9825031B1Methods of forming a high-k contact liner to improve effective via separation distance and the resulting devicesGLOBALFOUNDRIES INC·Filed 2016·Granted Nov 21, 2017·23 cites·16 claims
- 0794US9786545B1Method of forming ANA regions in an integrated circuitGLOBALFOUNDRIES INC·Filed 2016·Granted Oct 10, 2017·11 cites·20 claims
- 0894US9202751B2Transistor contacts self-aligned in two dimensionsGLOBALFOUNDRIES INC·Filed 2014·Granted Dec 1, 2015·13 cites·20 claims
- 0991US9691626B1Method of forming a pattern for interconnection lines in an integrated circuit wherein the pattern includes gamma and beta block mask portionsGLOBALFOUNDRIES INC·Filed 2016·Granted Jun 27, 2017·7 cites·18 claims
- 1091US9236437B2Method for creating self-aligned transistor contactsGLOBALFOUNDRIES INC·Filed 2014·Granted Jan 12, 2016·11 cites·8 claims
- 1191US9224617B2Forming cross-coupled line segmentsGLOBALFOUNDRIES INC·Filed 2014·Granted Dec 29, 2015·13 cites·18 claims
- 1290US11043418B2Middle of the line self-aligned direct pattern contactsGLOBALFOUNDRIES US INC·Filed 2019·Granted Jun 22, 2021·5 cites·19 claims
- 1389US9818623B2Method of forming a pattern for interconnection lines and associated continuity blocks in an integrated circuitGLOBALFOUNDRIES INC·Filed 2016·Granted Nov 14, 2017·6 cites·17 claims
- 1488US8839168B2Self-aligned double patterning via enclosure designGLOBALFOUNDRIES INC·Filed 2013·Granted Sep 16, 2014·11 cites·20 claims
- 1587US9779943B2Compensating for lithographic limitations in fabricating semiconductor interconnect structuresGLOBALFOUNDRIES INC·Filed 2016·Granted Oct 3, 2017·5 cites·15 claims
- 1687US9006100B2Middle-of-the-line constructs using diffusion contact structuresRASHED MAHBUB·Filed 2012·Granted Apr 14, 2015·9 cites·14 claims
- 1784US8987816B2Contact power railGLOBALFOUNDRIES INC·Filed 2014·Granted Mar 24, 2015·6 cites·20 claims
- 1884US8856715B1Capacitor designs for integrated circuits utilizing self-aligned double patterning (SADP)GLOBALFOUNDRIES INC·Filed 2013·Granted Oct 7, 2014·8 cites·20 claims
- 1983US8793627B1Via non-standard limiting parametersSTEPHENS JASON E·Filed 2013·Granted Jul 29, 2014·10 cites·21 claims
- 2081US9660040B2Transistor contacts self-aligned two dimensionsGLOBALFOUNDRIES INC·Filed 2015·Granted May 23, 2017·2 cites·6 claims
- 2179US10236350B2Method, apparatus and system for a high density middle of line flowGLOBALFOUNDRIES INC·Filed 2016·Granted Mar 19, 2019·3 cites·19 claims
- 2279US8946914B2Contact power railSTEPHENS JASON EUGENE·Filed 2013·Granted Feb 3, 2015·6 cites·13 claims
- 2378US9142513B2Middle-of-the-line constructs using diffusion contact structuresGLOBALFOUNDRIES INC·Filed 2015·Granted Sep 22, 2015·3 cites·20 claims
- 2475US10181420B2Devices with chamfer-less vias multi-patterning and methods for forming chamfer-less viasGLOBALFOUNDRIES INC·Filed 2017·Granted Jan 15, 2019·2 cites·10 claims
- 2574US10262941B2Devices and methods for forming cross coupled contactsGLOBALFOUNDRIES INC·Filed 2016·Granted Apr 16, 2019·2 cites·13 claims
- 2674US9502528B2Borderless contact formation through metal-recess dual cap integrationGLOBALFOUNDRIES INC·Filed 2014·Granted Nov 22, 2016·3 cites·13 claims
- 2773US10559503B2Methods, apparatus and system for a passthrough-based architectureGLOBALFOUNDRIES INC·Filed 2017·Granted Feb 11, 2020·1 cites·9 claims
- 2872US9812396B1Interconnect structure for semiconductor devices with multiple power rails and redundancyGLOBALFOUNDRIES INC·Filed 2016·Granted Nov 7, 2017·2 cites·8 claims
- 2972US9465907B2Multi-polygon constraint decomposition techniques for use in double patterning applicationsGLOBALFOUNDRIES INC·Filed 2014·Granted Oct 11, 2016·3 cites·20 claims
- 3071US9530689B2Methods for fabricating integrated circuits using multi-patterning processesGLOBALFOUNDRIES INC·Filed 2015·Granted Dec 27, 2016·2 cites·12 claims
- 3171US9412655B1Forming merged lines in a metallization layer by replacing sacrificial lines with conductive linesGLOBALFOUNDRIES INC·Filed 2015·Granted Aug 9, 2016·2 cites·20 claims
- 3270US10522403B2Middle of the line self-aligned direct pattern contactsGLOBALFOUNDRIES INC·Filed 2018·Granted Dec 31, 2019·1 cites·20 claims
- 3368US9472455B2Methods of cross-coupling line segments on a waferGLOBALFOUNDRIES INC·Filed 2014·Granted Oct 18, 2016·2 cites·20 claims
- 3464US8598633B2Semiconductor device having contact layer providing electrical connectionsTARABBIA MARC·Filed 2012·Granted Dec 3, 2013·3 cites·19 claims
- 3562US10741439B2Merge mandrel featuresGLOBALFOUNDRIES INC·Filed 2019·Granted Aug 11, 2020·0 cites·20 claims
- 3662US9576735B2Vertical capacitors with spaced conductive linesGLOBALFOUNDRIES INC·Filed 2014·Granted Feb 21, 2017·1 cites·20 claims
- 3759US10056373B2Transistor contacts self-aligned in two dimensionsGLOBALFOUNDRIES INC·Filed 2017·Granted Aug 21, 2018·0 cites·20 claims
- 3858US10340180B1Merge mandrel featuresGLOBALFOUNDRIES INC·Filed 2018·Granted Jul 2, 2019·0 cites·13 claims
- 3951US9461128B2Method for creating self-aligned transistor contactsGLOBALFOUNDRIES INC·Filed 2015·Granted Oct 4, 2016·0 cites·7 claims
- 4050US9436081B2Methods of modifying masking reticles to remove forbidden pitch regions thereofGLOBALFOUNDRIES INC·Filed 2014·Granted Sep 6, 2016·0 cites·20 claims
- 4150US2023352570A1Bipolar junction transistorGLOBALFOUNDRIES US INC·Filed 2022·Application pending·0 cites
- 4239US2019139823A1Methods of forming conductive lines and vias and the resulting structuresGLOBALFOUNDRIES INC·Filed 2017·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →