Inventor · disambiguated record
David John Seibert
Also filed as: SEIBERT DAVID · SEIBERT DAVID JOHN
4 granted patents·58 citations·filing 2006–2022
74Inventor score
Technology areasG06F
Top patents by PatentIndex Score
4 records- 0189US8782591B1Physically aware logic synthesis of integrated circuit designsCADENCE DESIGN SYSTEMS INC·Filed 2012·Granted Jul 15, 2014·32 cites·27 claims
- 0287US7559040B1Optimization of combinational logic synthesis through clock latency schedulingCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Jul 7, 2009·22 cites·37 claims
- 0379US10360341B2Integrated metal layer aware optimization of integrated circuit designsSYNOPSYS INC·Filed 2017·Granted Jul 23, 2019·4 cites·20 claims
- 0448US12450415B2Library design and co-optimization with a circuit designSYNOPSYS INC·Filed 2022·Granted Oct 21, 2025·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →