Inventor · disambiguated record
Da Yang
Also filed as: YANG DA · YANG DA-JIANG
25 granted patents·12 pending applications·78 citations·filing 2007–2020
94Inventor score
Files withQUALCOMM INC32INST OF MICROELECTRONICS CAS1SUN ZHI-QIANG1UNITED MICROELECTRONICS CORP1YIN HAIZHOU1
Top patents by PatentIndex Score
37 records- 0196US9871121B2Semiconductor device having a gap defined thereinQUALCOMM INC·Filed 2014·Granted Jan 16, 2018·25 cites·16 claims
- 0295US9799560B2Self-aligned structureQUALCOMM INC·Filed 2015·Granted Oct 24, 2017·13 cites·40 claims
- 0392US9953979B2Contact wrap around structureQUALCOMM INC·Filed 2015·Granted Apr 24, 2018·8 cites·14 claims
- 0484US10043796B2Vertically stacked nanowire field effect transistorsQUALCOMM INC·Filed 2016·Granted Aug 7, 2018·4 cites·33 claims
- 0584US9985014B2Minimum track standard cell circuits for reduced areaQUALCOMM INC·Filed 2016·Granted May 29, 2018·4 cites·26 claims
- 0681US10032678B2Nanowire channel structures of continuously stacked nanowires for complementary metal oxide semiconductor (CMOS) devicesQUALCOMM INC·Filed 2016·Granted Jul 24, 2018·3 cites·29 claims
- 0781US9653399B2Middle-of-line integration methods and semiconductor devicesQUALCOMM INC·Filed 2015·Granted May 16, 2017·3 cites·11 claims
- 0879US10497702B2Metal-oxide semiconductor (MOS) standard cells employing electrically coupled source regions and supply rails to relax source-drain tip-to-tip spacing between adjacent MOS standard cellsQUALCOMM INC·Filed 2017·Granted Dec 3, 2019·3 cites·26 claims
- 0977US9397007B2Method for manufacturing semiconductor structure through forming an additional layer inside opening of a photoresist layerINST OF MICROELECTRONICS CAS·Filed 2013·Granted Jul 19, 2016·3 cites·5 claims
- 1073US10090244B2Standard cell circuits employing high aspect ratio voltage rails for reduced resistanceQUALCOMM INC·Filed 2017·Granted Oct 2, 2018·2 cites·26 claims
- 1172US10079293B2Semiconductor device having a gap defined thereinQUALCOMM INC·Filed 2017·Granted Sep 18, 2018·1 cites·23 claims
- 1272US9620454B2Middle-of-line (MOL) manufactured integrated circuits (ICs) employing local interconnects of metal lines using an elongated via, and related methodsQUALCOMM INC·Filed 2014·Granted Apr 11, 2017·2 cites·18 claims
- 1372US8420492B2MOS transistor and method for forming the sameZHONG HUICAI·Filed 2011·Granted Apr 16, 2013·3 cites·23 claims
- 1470US9997360B2Method for mitigating layout effect in FINFETQUALCOMM INC·Filed 2016·Granted Jun 12, 2018·1 cites·15 claims
- 1570US8669160B2Method for manufacturing a semiconductor deviceYIN HAIZHOU·Filed 2012·Granted Mar 11, 2014·2 cites·10 claims
- 1666US9263279B2Combining cut mask lithography and conventional lithography to achieve sub-threshold pattern featuresQUALCOMM INC·Filed 2013·Granted Feb 16, 2016·1 cites·7 claims
- 1760US10763364B1Circuits having a diffusion break with avoided or reduced adjacent semiconductor channel strain relaxation, and related methodsQUALCOMM INC·Filed 2020·Granted Sep 1, 2020·0 cites·19 claims
- 1859US2020161189A1SELF-ALIGNED QUADRUPLE PATTERNING PROCESS FOR FIN PITCH BELOW 20nmQUALCOMM INC·Filed 2020·Application pending·0 cites
- 1958US10181403B2Layout effect mitigation in FinFETQUALCOMM INC·Filed 2018·Granted Jan 15, 2019·0 cites·8 claims
- 2054US10559501B2Self-aligned quadruple patterning process for Fin pitch below 20nmQUALCOMM INC·Filed 2016·Granted Feb 11, 2020·0 cites·14 claims
- 2153US10700204B2Circuits having a diffusion break with avoided or reduced adjacent semiconductor channel strain relaxation, and related methodsQUALCOMM INC·Filed 2018·Granted Jun 30, 2020·0 cites·25 claims
- 2248US9245971B2Semiconductor device having high mobility channelQUALCOMM INC·Filed 2013·Granted Jan 26, 2016·0 cites·45 claims
- 2348US7989804B2Test pattern structureUNITED MICROELECTRONICS CORP·Filed 2009·Granted Aug 2, 2011·0 cites·17 claims
- 2447US2016126137A1Combining cut mask lithography and conventional lithography to achieve sub-threshold pattern featuresQUALCOMM INC·Filed 2016·Application pending·0 cites
- 2545US2016093511A1Multigate transistor device and method of isolating adjacent transistors in multigate transistor device using self-aligned diffusion break (sadb)QUALCOMM INC·Filed 2014·Application pending·0 cites
- 2643US9502283B2Electron-beam (E-beam) based semiconductor device featuresQUALCOMM INC·Filed 2015·Granted Nov 22, 2016·0 cites·30 claims
- 2740US11152347B2Cell circuits formed in circuit cells employing offset gate cut areas in a non-active area for routing transistor gate cross-connectionsQUALCOMM INC·Filed 2018·Granted Oct 19, 2021·0 cites·26 claims
- 2840US2019296126A1Systems and methods for dummy gate tie-offs in a self-aligned gate contact (sagc) cellQUALCOMM INC·Filed 2018·Application pending·0 cites
- 2939US9859210B2Integrated circuits having reduced dimensions between componentsQUALCOMM INC·Filed 2015·Granted Jan 2, 2018·0 cites·16 claims
- 3039US2009042388A1Method of cleaning a semiconductor substrateSUN ZHI-QIANG·Filed 2007·Application pending·0 cites
- 3138US2017207313A1NANOWIRE METAL-OXIDE SEMICONDUCTOR (MOS) FIELD-EFFECT TRANSISTORS (FETs) (MOSFETs) EMPLOYING A NANOWIRE CHANNEL STRUCTURE EMPLOYING RECESSED CONDUCTIVE STRUCTURES FOR CONDUCTIVELY COUPLING NANOWIRE STRUCTURESQUALCOMM INC·Filed 2016·Application pending·0 cites
- 3238US2019304919A1Hybrid metal interconnect structures for advanced process nodesQUALCOMM INC·Filed 2018·Application pending·0 cites
- 3336US2017110541A1Nanowire channel structures of continuously stacked heterogeneous nanowires for complementary metal oxide semiconductor (cmos) devicesQUALCOMM INC·Filed 2016·Application pending·0 cites
- 3435US2016233159A1Integrated circuit device including multiple via connectors and a metal structure having a ladder shapeQUALCOMM INC·Filed 2015·Application pending·0 cites
- 3535US2017077090A1Multi-cell transistor device and method of making same with cut polyoxide process for self-aligned contactsQUALCOMM INC·Filed 2015·Application pending·0 cites
- 3634US2017338215A1Heterogeneous cell arrayQUALCOMM INC·Filed 2016·Application pending·0 cites
- 3734US2016141250A1Barrier structureQUALCOMM INC·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →